JPH0477093A - Acoustic equipment provided with howling preventing function - Google Patents

Abstract

PURPOSE:To prevent howling without deteriorating sound quality by providing a notch filter whose block center frequency is changed stepwise on a transmission line for an audio signal CONSTITUTION:Plural notch filters 411-41n each comprising a secondary 11R filter are provided between an A/D converter 7 and a D/A converter 8. The notch filters 411-41n have different blocking center frequencies and they are changed by selecting a multiplier coefficient. Thus, the notch filters 411-41n having the blocking center frequency are concentrated on a frequency band in which howling may take place and an audio signal liable to form a howling loop is surely interrupted.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to an acoustic device having an anti-howling function.

BACKGROUND ART A conventional acoustic device equipped with a howling prevention function that includes a pitch conversion device and a band rejection filter between a microphone and a speaker is disclosed in, for example, Japanese Patent Laid-Open No. 60-283.
It is disclosed in Japanese Patent No. 99 and is well known. In such a device, an audio signal from a microphone 1 is supplied to a pitch conversion device 3 via a microphone amplifier 2, as shown in FIG. The pitch conversion device 3 changes the frequency of the input audio signal. The output signal of the pitch conversion device 3 is supplied to a band rejection filter 4. The band rejection filter 4 is a comb-shaped filter having a characteristic in which pass rejection center frequencies are arranged at equal intervals as shown in FIG. The output signal of the band rejection filter 4 is amplified by a power amplifier 5 to drive a speaker 6.

In this configuration, when the audio signal from the microphone 1 is supplied to the pitch conversion device 3, the frequency of the audio signal is changed. The audio signal whose frequency has been changed passes through a band rejection filter 4, and then is further supplied to a speaker via a power amplifier 5 to become an acoustic output. When the output sound from the speaker 6 is received by the microphone 1, a loop that causes howling is formed. The frequency of the received audio signal is further changed by the pitch conversion device 3.

Now, if the frequency of the audio signal from the microphone 1 is fa as shown in FIG. Figure 11 (b
)). After one more loop and a time τ has elapsed, the pitch converter 3 converts the signal into an audio signal of frequency fc (FIG. 11(C)). If this frequency fc is the pass-stopping center frequency of the band-stop filter 4, then the frequency f
The audio signal c is blocked from passing by the band rejection filter 4, thereby preventing howling.

In such a conventional acoustic device equipped with a howling prevention function, in order to enhance the howling prevention effect, it is necessary to narrow the interval between each pass-stopping center frequency to prevent the signal that causes howling from passing through the band-stop filter 4. . However, when the interval between each pass-blocking center frequency is narrowed, there is a problem in that the gain in the narrowed frequency portion decreases and the sound quality deteriorates.

Summary of the Invention [Object of the Invention] An object of the present invention is to provide an audio device that can prevent howling without deteriorating sound quality.

[Structure of the Invention] The audio device of the present invention is an audio device that inputs an audio signal output from a microphone and has a howling prevention function, and includes a notch filter whose pass blocking center frequency changes over time in the audio signal transmission line. at least 1
It is characterized by having two.

Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

In the audio device shown in FIG. 1, an output signal from a microphone 1 is supplied to a microphone amplifier 2, and an A/D converter 7 is connected to the output of the microphone amplifier 2. A/
A DSP (digital signal processor) 9 is connected to the output of the D converter 7. The DSP 9 is configured as described below and is controlled by the microcomputer 10. D/A converter 8 is connected to the output of DSP9.
is connected, and the digital audio signal output from the DSP 9 is converted into an analog audio signal. D/
A speaker 6 is connected to the output of the A converter 8 via a power amplifier 5 as in the conventional case.

The configuration of the DSP 9 is schematically shown in FIG. 2.

That is, the digital signal from the A/D converter 7 is DS
It is supplied to the input interface 13 in P2. A data bus 14 is connected to the input interface 13, and this data bus 14 is connected to one of the data memory 12 for temporarily storing a group of signal data and a multiplier 15. A buffer memory 16 for holding coefficient data is connected to the other input of the multiplier 15.

A coefficient RAM 17 is connected to the buffer memory 16, and R
AM17 stores a plurality of coefficient data. One piece of coefficient data is sequentially read from a group of coefficient data stored in the RAM 17 in response to a timing signal from a sequence controller 20, which will be described later, and is supplied to and held in the buffer memory 16. The coefficient data held in buffer memory 16 is supplied to multiplier 15 . AL
U (Arlihmetlc Loglc Unlt)
18 is provided for accumulating the calculation output of the multiplier 15, one input is supplied with the calculation output of the multiplier 15, and the other is connected to the data bus 14. ALUI8
An accumulator 19 is connected to the calculation output of , and the output of the accumulator 19 is connected to the data bus 14 . A memory control circuit 22 is connected to the data bus 14 for controlling data writing and reading from an external memory 21 in order to create delay data.

Further, an output interface 23 is connected to the data bus 14, and the digital audio signal outputted from the output interface 23 is converted into a digital audio signal as an output signal of the DSP 9.
It is supplied to the A converter 7.

Interface 13.23, multiplier 15, coefficient RAM
17. The operation timing of ALUlg, accumulator 19 and memory control circuit 22 is determined by sequence controller 2.
Controlled by 0. The sequence controller 20 operates according to a processing program written in a program memory 24, and a keyboard 11 is connected to the microcomputer 10 to generate various commands by operation. The microcomputer 10 controls writing of coefficient data in the RAM 17 in response to key operations on the keyboard 11.

In this configuration, the microphone signal supplied to the A/D converter 7 is converted into digital audio signal data at every predetermined sampling period, and is supplied to the data memory 12 via the interface 13 and stored therein. On the other hand, the coefficient data read from the RAM 17 is supplied to the buffer memory 16 and held there. The sequence controller 20 controls the timing of reading data from the interface 13, the timing of selectively transferring data from the data memory 12 to the multiplier 15, the timing of outputting each coefficient data from the RAM 17, the multiplication operation timing of the multiplier 15, and the addition of ALUlg. Timings such as the operation timing, the output timing of the accumulator 19, and the timing of outputting the calculation result data from the interface 23 are determined. By taking these timings appropriately, for example, the coefficient data α1 is supplied from the buffer memory 16 and the data d1 from the data memory 12 are supplied to the multiplier 15, and in the multiplier 15, first, α1
・dl is calculated. When this α1·dl is calculated, θ+α1d1 is calculated in ALUlg, and the result of the calculation is held in the accumulator 19. Next, when coefficient data α2 is output from the buffer memory 16 and data d2 is output from the data memory 12, the multiplier 1
5, α2・d2 is calculated and the accumulator 1
α1·dl is output from 9, α1·d1+α2·d2 is calculated in ALUlg, and the result of the calculation is held in accumulator 19. By recirculating this, Σαru・dt is calculated.

In addition, when creating delay data for reflected sound, etc., the data is read from the data memory 12 and transferred to the data bus 14.
The signal is supplied to the memory control circuit 22 via. The memory control circuit 22 sequentially writes the data supplied to the external memory 21, and after writing, reads the data and uses it as delayed data when a predetermined delay time data has elapsed. The delayed data is supplied to the data memory 12 via the data bus 14, stored therein, and used in the arithmetic operation described above.

When the operation of the DSP 9 in the audio device according to the present invention is shown in an equivalent circuit, it is configured as a second-order IIR type filter as shown in FIG. In this filter,
A coefficient multiplier 31 and a delay element 32 are connected to an input end to which an audio data signal is supplied. Delay element 3
A coefficient multiplier 33 and a delay element 34 are connected to the output of 2. The output of the delay element 34 is further connected to a coefficient multiplier 35.
is connected. Each output of the coefficient multiplier 3], 33.35 is connected to an adder 36. A delay element 37 is connected to the output of the adder 36.

A coefficient multiplier 38 and a delay element 3 are connected to the output of the delay element 37.
9 is connected. A coefficient multiplier 40 is further connected to the outputs of the three delay elements. Each output of the coefficient multipliers 38, 40 is also connected to the adder 36.

Each delay time of delay elements 32, 34, 37, and 39 corresponds to one sampling period. Therefore, the data supplied to the multiplier 33 is data one sample earlier than the data supplied to the multiplier 31, and the data supplied to the multiplier 35 is data two samples earlier than the data supplied to the multiplier 31. It is data.

The same applies to multipliers 38 and 40.

The coefficient of the multiplier 31 is ao, the coefficient of the multiplier 33 is al, the coefficient of the multiplier 35 is a2, the coefficient of the multiplier 38 is bl, and the coefficient of the multiplier 40 is bl. These coefficients are aO−a2−
By setting A, a1=-bl-B, bl-any value, it operates as a notch filter. That is, since the pass-blocking center frequency changes depending on the setting of the values of A, B, and bl, A, B, and bl are set so as to reach the desired pass-blocking center frequency.

When only one such notch filter is formed by digital processing by the DSP 9, the DSP 9 operates as follows.

First, in the first step, input audio signal data dn is read from address n of the data memory 12, and R
The coefficient data a2 is read from the AM 17 and transferred to the buffer memory 16 to be multiplied by the multiplier 15. The ALU 18 adds 0 to the multiplication result a2.do in the third step, which is two steps after the first step, and the addition result is held in the accumulator 19.

In the second step, signal data d is obtained from address n-1 of the data memory 12. -1 is read out, and the multiplier 15 multiplies the read signal data d old and the coefficient data a1 newly read out from the RAM 17. The multiplication result a
1・dn-1 has ALU18 in the fourth step.
The value held in the accumulator 19 (the addition result of the third step) is added by the addition result, and the addition result is held in the accumulator 19. Next, in the third step, the input signal data IN is transferred from the interface 13 to address n-2 of the data memory 12 and the multiplier 15, and multiplied by the coefficient data aQ. The multiplication result a
The value held in the accumulator 19 (the addition result in the fourth step) is added to oφIN by the ALU 18 in the fifth step, and the addition result is held in the accumulator 19.

In the fourth step, the signal data dn+2 is read from address n+2 of the data memory 12, and the multiplier 15 multiplies the read signal data dn12 by the coefficient data b2 newly read from the RAM 17. The multiplication result b2 d n+2 is given by AL in the sixth step.
The value held in the accumulator 19 (the addition result of the fifth step) is added by U18, and the addition result is held in the accumulator 19. Then, in the fifth step, signal data d n is obtained from address n+1 of the data memory 12.
n+ is read out, and the multiplier 15 multiplies the read signal data d n41 and the read coefficient data b1. In the seventh step, the value held in the accumulator 19 (the addition result in the fifth step) is added to the multiplication result b+·d nil by ALυ]8, and the addition result is held in the accumulator 19 as output data.

Each coefficient data a6-a2, s, , bl is read from the internal memory (not shown) of the microcomputer 10 and transferred to a predetermined coefficient data area of the RAMI 7. Further, this coefficient data area contains coefficient data EIQ=a2 and bl.

A27 al, aol bl are a plurality of data groups with different values of A and B described above, where bl is one data group.

The data is stored in the order of bl starting from address 1.

In order to configure a plurality (5) of notch filters (first to fifth notch filters) having different pass-blocking center frequencies, each one has coefficient data a2 +
Coefficient data groups Fl, F2 . al , ao + bl , bl . ~F5. F, +ΔFF2+ΔF2.・
...F4+5ΔF4. F5+5ΔF5 are stored in the order of reading. Data group F1+ F2. F3. F4
．． FS is each passage blocking center frequency fl, f2° f3 . This is a data group from which f, , f5 are obtained, and each pass-blocking center frequency is taken as a reference frequency. Note that fl < f2 < f3 < f4 < f5.

Data group F1 + ΔF1 is frequency f1 with unit change width Δf1
This is a data group when the frequency obtained by adding up is set as the pass-blocking center frequency. The data group F1+2ΔF1 is a data group when the frequency obtained by adding the variation width 2×Δf1 to the frequency f1 is set as the pass-blocking center frequency.

Similarly, data group F】+3ΔF+, F++4ΔF+, F
+ +5ΔF1 is a change width of 3×Δfl in frequency f1,
This is a data group when the frequency obtained by adding 4XΔf1 and 5xΔf1 is set as the pass-blocking center frequency. Other data group F
2. F3. F4. The same applies to F5. Also, the change width per unit time △fl+ △f2. △f3. △f4.
Δf5 is set independently, and does not need to all have the same value. Sequence controller 2 when reading
0 timing signal, sequentially from address 1,
In other words, the coefficient data a2゜al, a□ of data IF+
l b2 r b I , then F2 coefficient data a2 , al , ao 1 b2 , bl
The coefficient data is read out as shown in """.Then, the coefficient data a2+ al, a of the data group F5+5ΔF5
o, b2. When bl is read out, the coefficient data of the data group F1 at address 1 is read out again.

Each of the read coefficient data groups F1 to F5 is multiplied by the sampling signal data group at the first timing, and each of the coefficient data groups F1+ΔF1 to F5+ΔF5 is multiplied by the next sampling signal data group at the second timing. below,
Coefficient data group F1 12△F1 to F5+2ΔF5 each,
FI+3ΔF1~F5+3ΔF5 each, F1+4ΔF1
~F5 14ΔF5 each, F1+5ΔFl −F5 +5
The same goes for each of ΔF5, and this is repeated.

Therefore, the passage blocking center frequencies of the first to fifth notch filters are f1 to f5 for the coefficient data groups F1 to F5 read out as shown in FIG. 5, and coefficient data group F1+Δ.
fl +△f, -f5+△ for F1~F5+△F5
f5. Coefficient data 2! $ F1+2ΔF1~F5+2Δ
f1+2Δf1 to f5+2Δf5 for F5, f1+ for coefficient data group F1+3ΔF1 to F5+3ΔF5
3△f~f5+3△f5, coefficient data group F1+4ΔF1
~F5+4ΔF5 for f1+4△f1~f514△
f5, coefficient data group F1+5ΔF1 to F5+5ΔF5, becomes f1+5Δf1 to f5+5Δf5, and this is repeated, so the pass-blocking center frequency of each notch filter changes with the passage of time. For example, the first notch filter whose reference frequency is the pass-blocking center frequency f1 has the characteristics of the pass-blocking center frequency fl as shown in FIG. Characteristics of f1 ■1 Characteristics of pass blocking center frequency f1+3Δf1 ■1 Pass blocking center frequency fl
Characteristics of +4△f1 ■1 pass blocking center frequency fl +5△
The characteristic of f1 changes as shown in ■.

Regarding the second to fifth notch filters, the reference frequency f2. Only f,,f,,f5 are shown, but the first
Similar to a notch filter, the pass blocking center frequency changes over time.

In the embodiments described above, the frequency change widths of the first to fifth notch filters are not necessarily the same.

Generally, the frequency range where howling is likely to occur (for example, 1
For frequencies from kHz to 4 kHz, more notch filters may be formed than for other frequencies to reduce the range of change in the pass-blocking center frequency and to increase the speed of frequency change per unit time. For example, 1kHz to 4
Let the change width of the pass blocking center frequency of kHz be 2 Hz, and the frequency change width per unit time be IHz.

Furthermore, in the embodiments described above, the present invention is configured using the DSP 9, but the present invention is not limited thereto. For example, as shown in FIG. 7, between the A/D converter 7 and the D/A converter 8, a plurality of notch filters 411, 412, . It may be provided. This notch filter 411.412...41
n have different pass-blocking center frequencies, and the control circuit 4
2, the passage blocking center frequency is changed by switching and changing the multiplication coefficient. Furthermore, these notch filters may be configured as analog circuits.

FIG. 8 shows another embodiment of the invention. In this main tube device, a frequency modulation circuit 43 is further provided in addition to the device shown in FIG. The frequency modulation circuit 43 has a memory (not shown), and changes the frequency of the audio signal by writing a digital audio signal into the memory and reading out the digital audio signal written into the memory at a speed different from the writing speed. It is. Regarding this frequency modulation circuit 43, for example, JP-A-61. -118797 publication and Japanese Patent Application Laid-Open No. 6112109
Since it is disclosed as a pitch control device in Japanese Patent No. 6, it will not be described in detail here. Moreover, such a frequency modulation circuit can be used as a DS
It may also be formed of P. In this case, the writing and reading of data to and from the external RAM 21 shown in FIG. 2 is controlled by the memory control circuit 22.

Furthermore, the frequency modulation circuit may be constructed from a known analog circuit.

Effects of the Invention As described above, in the acoustic device equipped with the howling prevention function of the present invention, the transmission line of the audio signal from the microphone is equipped with a notch filter whose pass-blocking center frequency changes over time. Notch filters having pass-blocking center frequencies can be concentrated in a band, thereby reliably blocking audio signals that would form a howling loop. Therefore, howling can be prevented without deteriorating sound quality.

[Brief Description of the Drawings] Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a block diagram showing the configuration of the DSP in the device shown in Fig. 1, and Fig. 3 shows the same operation as the DSP. FIG. 4 is a diagram showing the storage state of the coefficient data group in the RAM in the DSP; FIG. 5 is a diagram showing the pass-blocking center frequencies of the first to fifth notch filters; FIG. The figure shows the passage blocking characteristics of the first to fifth notch filters, and the figure shows the passage blocking characteristics of the first to fifth notch filters.
and FIG. 8 are block diagrams showing other embodiments of the present invention,
FIG. 9 is a block diagram showing a conventional acoustic device equipped with a howling prevention function, and FIG. 10 is a block diagram showing howling prevention function in the conventional device shown in FIG. FIG. 11 is a diagram showing the frequency change of the audio signal when a loop is formed in the conventional device shown in FIG. 9. Explanation of symbols of main parts 1...Microphone 9...DSP]0...Microcomputer 31.33, 35, 38.40...Multiplier 32.34
, 37.39...Delay element 36...Adder Fig. 1

Claims (4)

[Claims] (1) An audio device with a howling prevention function that inputs an audio signal output from a microphone,
An acoustic device having a howling prevention function, characterized in that the audio signal transmission line includes at least one notch filter whose pass blocking center frequency changes over time. (2) The audio device according to claim 1, wherein the audio signal transmission line is provided with a frequency modulation circuit. (3) The acoustic device according to claim 1, wherein the notch filter is an IIR type filter. (4) The acoustic device according to claim 3, wherein the IIR type filter is formed by arithmetic processing in a digital signal processor.