JP3180371B2 - Signal delay device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION This invention relates to a signal delay device Ru delays the audio signal and tone signal.

[0002]

2. Description of the Related Art Shift registers and digital signal processors (DSPs) have been put into practical use as devices for delaying time-series signals such as audio signals. Devices using the shift register include a comb filter, an echo, a reverb circuit, and the like. In addition, the DSP quantizes a time-series analog signal at each sampling timing and writes / reads a digitized signal to / from a memory by a high-speed microprocessor in a first-in first-out (FIFO) manner, thereby delaying the number of storage stages of the memory. Is realized. Various complicated combinations of delays and feedbacks can be realized by the program. Approximately 40k to maintain the sound quality to delay the tone signal
Shift / sample at a frequency of Hz. Therefore, 1
In order to obtain a delay time on the order of seconds, 40,000 storage stages are required. Further, in the case of realizing a filter effect by combining a plurality of delay circuits as well as a simple delay, many such shift registers and storage areas for delay are required.

[0003] The delay time of a musical tone varies depending on the type of the musical tone and the effect to be imparted, and the type of the musical tone (tone color, etc.)
Is often changed. When the effect is changed, the number of delay stages is changed. Therefore, if only the effect is changed without clearing the stored contents, it causes noise. For this reason,
At the time of effect switching, input / output with respect to the system is prohibited for a while so that noise does not occur, or all stored contents are cleared.

[0004]

However, in the method of cutting off the input / output, if the number of new delay stages is set to N, all the stored contents can be cleared by cutting off the N clock input. Cleared contents (0)
However, there is a disadvantage that the total time effect of 2N is not applied since only the output is performed. Although a method of clearing the memory in a short time has also been proposed, there is a drawback that dedicated hardware is required and the configuration is complicated.

According to the present invention, when the delay time is changed with a simple configuration,
It is an object of the present invention to provide a signal delay device capable of preventing noise at the time of signal switching .

[0006]

Means for Solving the Problems The invention according to claim 1 is a closed loop.
A plurality of delay means connected in a loop
A signal is input to the input unit provided on the
A signal delay device for extracting a signal from an output unit provided
Output of each delay means when signal generation is instructed
Is masked by the time corresponding to the delay time of each delay means.
Means are provided.

[0007] The invention of claim 2 is the invention according to claim 1.
The plurality of delay means can set a delay time,
When the signal generation is instructed, the delay time of each delay means is set.
It is characterized by being specified.

[0008]

The signal delay device according to the present invention includes a plurality of delay means.
Connect to a closed loop, input a signal to this closed roof,
After processing, this is output. The delay means can be realized by a shift register or a DSP . A new signal
When input , old (unnecessary) data is still stored in the delay means. This old data is replaced with new data when the new delay time has elapsed. However, during this time, old data is output. Therefore, during this time , only the output is masked in each delay means . This makes it possible to clear the old data for each delay unit while repeating the normal operation, and to apply the effect of new data in a time shorter than the delay time of the entire closed loop .

Each delay means can set a delay time.
The delay time is set when a new signal is input.
You. Thus, the delay time is set when a new signal is input
Even if it is changed, by masking <br/> delay time only the output of the delay means for each delay means it can also resume delay processing of the signal in the shortest time in a complex circuit.

[0010]

FIG. 1 shows a mask processing which is the basis of the present invention.
This is the echo effect circuit to be executed. This circuit is a combination of a delay circuit composed of a shift register and a feedback circuit.

A switch 4 is connected to the output side of the N-stage shift register 1. The switch 4 outputs a signal through the switch 4 and performs feedback through an attenuator 3. The output of the attenuator 3 is input to the adder 2 connected to the input side of the shift register 1. Adder 2
, A feedback signal and an input signal are input, added, and input to the first-stage register of the shift register 1. The switch 4 is connected to a counter 5. The counter 5 receives the number of stages N set in the shift register 1 and also receives the sampling clock φ. The switch 4 is normally closed, but when the number of stages of the shift register is changed, a new number N of stages is inputted to the counter 5, and the counter 5 opens the switch 4 until the counting of this N is completed. , The output from the shift register 1 is cut off. As a result, all old data stored in the shift register 1 at the time of switching the number of stages is discarded, and new data is output.

Although noise caused by reading of old data can be prevented by the above-described embodiment, if reading is stopped or restarted suddenly, the data becomes discontinuous before and after reading. This causes click noise.

Therefore, in the circuit shown in FIG. 2, the reading of old data is not stopped or restarted abruptly, but a multiplier is used in place of the gate, and the passing rate is gradually increased as shown in FIG. To be attenuated and returned. As a result, a click sound at the time of effect switching can be eliminated.
In this embodiment, the multipliers are provided on both the input side and the output side, but only one of them can fulfill its function.

FIG. 3 is a diagram showing a configuration of an electronic musical instrument provided with an effect device having a plurality of delay circuits. The performance operator 10 is connected to the control unit 11. The controller 11 is connected to the waveform generator 12 and the gate timing generator 16. The waveform generator 12 is a circuit that generates a musical tone waveform signal based on the operation contents of the performance operator 10 and the like. The gate timing generator 16 (16-1, 16-2, 16-3) includes gates G ₁ , G ₂ , G ₂ , G ₂ , which pass / block the outputs of the delay circuits D ₁ , D ₂ , D ₃ provided in the effect device. a counter for counting the interruption time of the G _3. The output of the waveform generator 12 is output after passing through the effect device. Delay unit 13 effects apparatus having a delay circuit D _1, the all-pass filter unit 14 and the delay circuit D ₃ having a delay circuit D ₂
And a low-pass filter section 15 having the following. Gates G ₁ , G ₂ , G ₃ are connected to the output side of each delay circuit D ₁ , D ₂ , D ₃ , respectively. The gates G ₁ , G ₂ and G ₃ are connected to the gate timing generator 16-
It is opened and closed by 1, 16-2 and 16-3. The number of delay stages N ₁ , N ₂ , N ₃ of the delay circuits D ₁ , D ₂ , D ₃ is given by the control unit 11. Further, the control unit 11 gives the gains α and β of the amplifiers of the all-pass filter unit 14 and the low-pass filter unit 15 and also gives a clock signal φ for synchronizing the operation timing of each circuit unit.
N ₁ , N ₂ , N ₃ , α, β vary depending on the musical tone (tone color, pitch, etc.).

The performance operator 10 is operated (key-on).
The control section 11 outputs N ₁ , N ₂ , N ₃ , α, and β for the musical tone every time. These N ₁ , N ₂ , and N ₃ are also input to the gate timing generators 16-1, 16-2, and 16-3.
The gate cutoff time for effect switching by this is counted. This signal is shown in FIG. Performance control 10
In response to the operation, the generation of a musical tone waveform signal is started and input to the effect device. At the same time, the gate timing generator 16-1,
Gate control signals g ₁ , g ₂ , g ₃ from 16-2, 16-3
As a result, the outputs of the delay circuits D ₁ , D ₂ , D ₃ are cut off by the delay time (the number of clocks), and old data is discarded. At this time, input of new data is continued. Thereafter, the gates are sequentially opened from the one with the shortest delay time, and the operation is performed so that the entire circuit is reconfigured.

In the configuration shown in FIG. ₁ , for example, when the number of delay stages N ₁ of the delay circuit D ₁ is shorter than the number of delay stages N ₂ of the delay circuit D ₂ , the output of the delay circuit D ₁ is N ₂ cycles from key-on. during characteristics effect subsequent all-pass filter is outputted through the multiplier coefficient α without being tone becomes after N ₂ passed the filter effect is applied, the time of N ₂ cycles obtained as at least an output , And the delay in the operation of this filter does not cause a problem in hearing.

As described above, according to the present invention, a closed loop
New signals are input to the delay means connected to
Until the delay time of each delay means elapses
Because it can only clear signal masks the outputs of all the memory be rather Na equipped with hardware such as clearing can resume the application of the delay effect in the shortest time.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an echo effect circuit that executes a mask process which is a basis of the present invention.

FIG. 2 is a diagram showing an example in which the echo effect circuit is configured using a multiplier.

FIG. 3 is a configuration diagram of an electronic musical instrument according to an embodiment of the present invention .

[Explanation of symbols]

 1-shift register, 4-gate, 5-counter.

Claims (2)

(57) [Claims] 1. A plurality of delay means connected in a closed loop.
Inputting a signal to an input unit provided on the closed loop
And extracts a signal from an output unit provided on the closed loop.
A signal delay device that delays the output of each delay means when a signal generation is instructed.
A signal delay device comprising: means for masking for a time corresponding to the delay time of the extension means . 2. The delay means can set a delay time.
When the signal generation is instructed, the delay means
The signal delay device according to claim 1, wherein a delay time is set.