EP0479410A1 - Sound field compensating apparatus for a small room - Google Patents
Sound field compensating apparatus for a small room Download PDFInfo
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- EP0479410A1 EP0479410A1 EP91303677A EP91303677A EP0479410A1 EP 0479410 A1 EP0479410 A1 EP 0479410A1 EP 91303677 A EP91303677 A EP 91303677A EP 91303677 A EP91303677 A EP 91303677A EP 0479410 A1 EP0479410 A1 EP 0479410A1
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- sound
- signal
- data
- compensating
- multiplier
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04R—LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; DEAF-AID SETS; PUBLIC ADDRESS SYSTEMS
- H04R3/00—Circuits for transducers, loudspeakers or microphones
- H04R3/04—Circuits for transducers, loudspeakers or microphones for correcting frequency response
Definitions
- the present invention relates to a sound field compensating apparatus for application to a small room such as the indoor space of a vehicle.
- the prior art apparatus produces a compensation signal which is reverse in the phase to the reflected sound of an original sound and added to a signal of the original sound.
- the reflected sound of the original sound will thus be offset by a compensation sound produced from a loudspeaker by the addition signal.
- the compensation sound of reverse phase for offsetting the reflected sound of the original sound also produces a reflected sound which causes a dip in the lower frequency range from 70 to 80 Hz.
- the compensation for unwanted effects in the sound field will be imperfect.
- a sound field compensating apparatus for compensating the sound field in a small room for undesired effects caused by the reflected sounds of a speaker sound, comprising compensating means for producing a compensation signal through delaying and amplitude controlling the original sound signal so that a sound wave developed from the compensation signal can be reverse in the phase to the reflected sound of the original sound, wherein,the compensating means is produced another compensation signal so that its sound wave can be reverse in the phase to the reflected sound of the preceding compensating sound.
- a compensating sound developed by the compensation signal is emitted to offset the reflected sound of the original sound at the listening point and then, another compensating sound triggered by a like compensation signal is emitted to offset the reflected sound of the compensating sound at the listening point. This procedure will be repeated for further compensation.
- Fig. 2 illustrates an audio system provided with a sound field compensating apparatus according the present invention.
- an audio signal generated at an analog audio signal source 1 e.g. a tuner or a taperecorder
- an A/D converter 2 which is coupled at output to a digital signal processor 3 (abbreviated to DSP).
- the DSP 3 is arranged as described later and controlled by a microcomputer 4.
- the output of the DSP 3 is coupled to a D/A converter 5 where a digital output from the DSP 3 is converted back to an analog audio signal.
- the output of the D/A converter 5 is coupled via an amplifier 6 to a loudspeaker 7. If the input is derived from a digital audio signal source, e.g. a digital audio taperecorder (DAT), it will be fed directly to the DSP 3 with no use of the A/D converter 2.
- DAT digital audio taperecorder
- the arrangement of the DSP 3 is also portrayed in Fig. 3.
- a digital signal from the A/D converter 2 is supplied to an input interface 13 of the DSP 3.
- the input interface 13 is coupled to a data bus 14 which is connected to a data memory 12 for temporary storage of a series of signal data and to one of the two inputs of a multiplier 15.
- the other input of the multiplier 15 is coupled to a buffer memory 16 for holding coefficient data.
- the buffer memory 16 is coupled at the other end to a coefficient RAM 17 which carries a multiplicity of coefficient data.
- the RAM 17 Upon receiving a timing signal from a sequence controller 20, which will be described later, the RAM 17 delivers a corresponding group of the coefficient data in sequence to the buffer memory 16 where they are retained. Then, the coefficient data are fed to the multiplier 15.
- An arithmetic logic unit 18 is provided for accumulation of numerical outputs from the multiplier 15 and coupled at one of the two inputs with the multiplier 15 and at the other input with the data bus 14.
- the output of the ALU 18 is coupled to an accumulator 19 which is connected at output end to the data bus 14.
- the data bus 14 is also connected with a memory controller circuit 22 which controls data read and write action on an external memory 21 for producing delay data.
- the memory bus 14 is further communicated with an output interface 23.
- a digital audio signal from the output interface 23 is then supplied as the output signal of the DSP 3 to the D/A converter 5.
- the timing for activating the two interfaces 13 and 23, the multiplier 15, the coefficient RAM 17, the ALU 18, the accumulator 19, and the memory controller circuit 22 is all controlled by the sequence controller 20.
- the sequence controller 20 is actuated in accordance with a processing program memorized in a program memory 24 and also, in response to an instruction from the microcomputer 4.
- the microcomputer 4 is coupled with a keyboard 8 for entry of various instructions through key operation. In response to key operations with the keyboard 8, the microcomputer 4 controls writing of coefficient data into the RAM 17.
- an analog audio signals is converted at each predetermined sampling period into a digital audio signal data which is fed via the interface 13 to the data memory 12 for storage.
- a coefficient data retrieved from the RAM 17 is transferred to the buffer memory 16 for storage.
- the sequence controller 20 provides operational timing for reading data from the interface 13, for selectively transferring data to the multiplier 15, for retrieving each coefficient data from the RAM 17, for performing multiplication on the multiplier 15, for performing addition on the ALU 18, for releasing data from the accumulator 19, and for delivering calculated results from the interface 23.
- Each step of the arithmetic operation e.g. filter calculation, is triggered by a relevant timing signal.
- an audio signal data from the interface 13 is supplied via the data bus 14 to the data memory 12 where it is stored.
- a series of the signal data are then retrieved in sequence from the data memory 12 and fed to the multiplier 15. Also, coefficient data are in sequence retrieved from the RAM 17 and fed to the buffer memory 16 for storage. The coefficient data from the RAM 17 are also supplied to the multiplier 15 for multiplication with the signal data from the data memory 12. Resultant multiplication values are then accumulated with the previous values (held in the accumulator 19) by the ALU 18. Subsequently, the resultant sum values are stored in the accumulator 19.
- delay data For production of delay data for application to reflected sound, data from the data memory 12 is fed via the data bus 14 to the memory controller circuit 22.
- the memory controller circuit 22 writes the supplied data to the external memory 21.
- a given length of delay time for example, ⁇
- the memory controller circuit 22 reads out the data and releases them as delayed data.
- the delayed data is then transferred via the data bus 14 to the data memory 12 for storage to use in the arithmetic operation mentioned above.
- the foregoing arrangement of the DSP 3 is also expressed by an equivalent circuit which is mainly consisted of an LPF 25 and a digital filter circuit 26 as shown in Fig. 4.
- the LPF 25 is constructed in the form of a second IIR filter as illustrated in Fig. 5.
- the LPF 25 contains a coefficient multiplier 31 and a delay element 32 both coupled to the input from which an audio data signal is intaken.
- the output of the delay element 32 is coupled to another coefficient multiplier 33 and another delay element 34.
- the output of the delay element 34 is coupled to a further coefficient multiplier 35.
- the outputs of their respective coefficients multipliers 31, 33, and 35 are all coupled to an adder 36.
- the output of the adder 36 is coupled to a delay element 37.
- the output of the delay element 37 is coupled to a coefficient multiplier 38 and another delay element 39.
- the output of the delay element 39 is coupled to a coefficient multiplier 40. Then, the outputs of the two coefficient multipliers 38 and 40 are connected to the adder 36.
- Each delay time of the delay elements 32, 34, 37, and 39 corresponds to one sampling period. Accordingly, the data to be supplied to the multiplier 33 is a data before the data to be supplied to the multiplier 31 by one sample,and the data to be supplied to the multiplier 35 is a data before the data to be supplied to the multiplier 31 by two samples. This is also the case with the multipliers 38 and 40.
- the delay time data are produced by arithmetic operation, e.g. multiplication, in the DSP 3 in accordance with timing signals from the sequence controller 20.
- the coefficient data assigned to the LPF 25 are retrieved in sequence from the RAM 17 and fed across the buffer memory 16 to the multiplier 15 of the DSP 3 where they are multiplied by the factor of signal data, which stands for the performance of the multipliers 31, 33, 35, 38, and 40 of the LPF 25. Hence, the frequency characteristics of the LPF 25 are determined by the coefficient data supplied.
- the digital filter circuit 26 may be an IIR filter comprising an adder 41, a coefficient multiplier 42, and a delay element 43, as shown in Fig. 6.
- An input audio signal is transmitted across the adder 41 directly to the output of the circuit 26 and also, to the coefficient multiplier 42.
- the coefficient multiplier 42 the input signal is multiplied by a coefficient -k where k is determined as 0 ⁇ k ⁇ 1.
- An output signal from the coefficient multiplier 42 is fed to the delay element 41 where it is delayed by a delay time ⁇ .
- the delay time ⁇ is equal to 2L/c where L is the distance from a reflection point to a listening point in the narrow room (e.g. between a tow board 52 and a listening position P portrayed in Fig.
- the delay time ⁇ is produced by using the external memory 21 in the DSP 3.
- a resultant output signal of the delay element 43 is supplied to the adder 41 where it is added to the input audio signal as the original signal.
- the multiplier 42 of the digital filter circuit 26 is realized by a procedure in which the coefficient data k is retrieved from the RAM 17 and fed across the buffer memory 16 to the multiplier 15 where it is multiplied by the signal data.
- a pulse signal as an original audio signal A(0) is supplied as shown in Fig. 7-a
- a sound B(0) is produced from the speaker 7 as shown in Fig.7-b and reaches a listening point.
- the reflected sound B(1) to the sound B(0) also reaches the listening point after time ⁇ elapses.
- a first compensation signal A(1) is generated in the digital filter circuit 26 through multiplying the original audio signal A(0) by the coefficient data -k and delaying the result of the multiplication by the time ⁇ .
- a sound B(1)′ produced from the speaker 7 by the first compensation signal A(1) is reverse in the phase to the reflected sound B(1), as shown in Fig. 7-c, and will thus offset the reflected sound B(1) at the listening point.
- the sound B(1)′ also develops its reflection B(2) which arrives at the listening point the time ⁇ later.
- the filter circuit 26 again actuates for multiplication of the first compensation signal A(1) by the coefficient data -k and delaying the result of the multiplication by the time ⁇ , producing a second compensation signal A(2).
- a resultant sound B(2)′ from the speaker 7 triggered by the second compensation signal A(2) is reverse in the phase to the reflected sound B(2) and will thus offset B(2). It is now understood that a reflection B(3) of B(2)′ can also be eliminated by the same manner as described.
- the digital filter circuit 26 may be an FIR filter comprising two delay elements 46 and 47, two coefficient multipliers 48 and 49, and an adder 50, as shown in Fig. 8.
- an input audio signal is fed to the delay element 46 and the adder 50.
- An output signal from the delay element 46 is transferred to the coefficient multiplier 48 and also, to the delay element 47 where it is delayed once again.
- An output signal of the delay element 47 is fed to the coefficient multiplier 49.
- the output signals of their respective coefficient multipliers 48 and 49 are then supplied to the adder 50.
- the delay time ⁇ of the delay elements 46 and 47 is equal to 2L/c where L is the distance from a reflection point to a listening point in a small room and c is the velocity of sound.
- the coefficient of the multiplier 48 is -k1 and the coefficient of the multiplier 49 is +k2, on condition that 0 ⁇ k1 ⁇ 1 and 0 ⁇ k2 ⁇ 1.
- a low frequency component of the original sound passing the LPF 25 is delayed by ⁇ at the delay element 46.
- a delayed signal is then fed to the multiplier 48 where it is multiplied by -k1 for generating a first compensation signal. Also, the delayed signal from the delay element 46 is further delayed by ⁇ at the delay element 47.
- a 2 ⁇ delay signal is then supplied to the multiplier 49 where it is multiplied by k2 for generating a second compensation signal. Accordingly, the adder 50 receives the first and second compensation signals as well as the low frequency component of the original sound directly transferred from the LPF 25.
- a first compensation signal A(1) is generated in the digital filter circuit 26 through delaying the original signal A(0) by the time ⁇ and multiplying a delayed signal by -k1.
- a resultant sound B(1)′ from the speaker 7 triggered by the first compensation signal A(1) is reverse in the phase to a reflected sound B(1) and will thus offset the reflection B(1) at the listening point.
- the original signal A(0) is delayed by 2 ⁇ and a delayed signal is then multiplied by k2 to a second compensation signal A(2).
- a resultant sound B(2)′ from the speaker 7 triggered by the second compensation signal A(2) is reverse in the phase to a reflection B(2) and will thus offset B(2) at the listening point.
- Multi-channel audio signals will be processed with equal success using the combination of an LPF and a digital filter circuit for each channel.
- the LPF and the filter circuit are controlled for producing compensation signals by the digital operation with the DSP in the described embodiment, they may be arranged in the form of an analog circuit.
- the sound field compensating apparatus of the present invention produces a compensation signal through delaying and amplitude controlling the original signal so that the compensation signal when shifted to a sound wave becomes reverse in the phase to a reflected sound wave and also, a further compensation signal which when shifted to a sound wave, becomes reverse in the phase to the reflected sound of a sound developed by the primary compensation signal. Accordingly, the unwanted reflected sound of the compensation signal sound which is emitted for offsetting the reflected sound of the original sound is successfully eliminated by a further compensation signal and thus, dip in the low range of sound pressure frequencies is diminished at the listening point in a small room where acoustic characteristic will in turn be enhanced.
Abstract
A sound field compensating apparatus for a small room is provided so that a compensating sound developed by a compensation signal produced therein is emitted to offset the reflected sound of an original speaker sound at the listening point in a small room where reflection of sounds is not avoided and then, another compensating sound triggered by a like compensation signal is emitted to offset the reflected sound of the compensating sound at the listening point. This procedure is to be repeated for further compensation. Hence, unwanted dip in the frequency characteristic with sound pressure can be diminished at the listening point and the sound field will be improved.
Description
- The present invention relates to a sound field compensating apparatus for application to a small room such as the indoor space of a vehicle.
- When an audio system is installed in a narrow room such as the indoor space of a vehicle, the original signal or direct sound from a loudspeaker(s) is disturbed by reflected sounds during reproduction. Accordingly, peak and dip in a frequency characteristic with sound pressure appear at every listening point of the sound field thus causing declination in the acoustic condition. For example, in the vehicle indoor space shown in Fig. 1, original sound emitted from a rear speaker(s) SP is reflected on a
tow board 52 provided in front of afront seat 51 causing acoustic interference. Hence, dip in the frequency characteristic with the sound pressure will occur. For compensation of such a sound field, a compensating apparatus has been developed as disclosed in Japanese Patent Laid-open Publication 60-254996 (1985). The prior art apparatus produces a compensation signal which is reverse in the phase to the reflected sound of an original sound and added to a signal of the original sound. The reflected sound of the original sound will thus be offset by a compensation sound produced from a loudspeaker by the addition signal. - However, the compensation sound of reverse phase for offsetting the reflected sound of the original sound also produces a reflected sound which causes a dip in the lower frequency range from 70 to 80 Hz. Thus, the compensation for unwanted effects in the sound field will be imperfect.
- It is an object of the present invention to provide a sound field compensating apparatus for application to a small room, in which unwanted dip in the frequency characteristic with the sound pressure at a listening point is diminished and the sound field will be improved.
- A sound field compensating apparatus according to the present invention is provided for compensating the sound field in a small room for undesired effects caused by the reflected sounds of a speaker sound, comprising compensating means for producing a compensation signal through delaying and amplitude controlling the original sound signal so that a sound wave developed from the compensation signal can be reverse in the phase to the reflected sound of the original sound, wherein,the compensating means is produced another compensation signal so that its sound wave can be reverse in the phase to the reflected sound of the preceding compensating sound.
- In the operation of the sound field compensating apparatus for a small room of the present invention, a compensating sound developed by the compensation signal is emitted to offset the reflected sound of the original sound at the listening point and then, another compensating sound triggered by a like compensation signal is emitted to offset the reflected sound of the compensating sound at the listening point. This procedure will be repeated for further compensation.
- Embodiments of the present invention will now be described by way of example only and with reference to the accompanying drawings, in which:-
- Fig. 1 is a view showing the reflection of an original sound in the indoor space of a vehicle;
- Fig. 2 is a block diagram of an audio system equipped with a sound field compensating apparatus for a small room according to the present invention;
- Fig. 3 is a block diagram showing the schematic arrangement of a DSP in the apparatus portrayed in Fig. 2;
- Fig. 4 is a block diagram of a circuit realizing by the arithmetic operation of the DSP;
- Fig. 5 is a block diagram showing the arrangement of an LPF;
- Fig. 6 and 8 are block diagrams showing different digital filter circuits; and
- Fig. 7 is waveform diagram showing the operation in the sound field compensating apparatus of the present invention.
- Fig. 2 illustrates an audio system provided with a sound field compensating apparatus according the present invention. In the apparatus, an audio signal generated at an analog
audio signal source 1, e.g. a tuner or a taperecorder, is supplied to an A/D converter 2 which is coupled at output to a digital signal processor 3 (abbreviated to DSP). The DSP 3 is arranged as described later and controlled by amicrocomputer 4. The output of theDSP 3 is coupled to a D/A converter 5 where a digital output from theDSP 3 is converted back to an analog audio signal. The output of the D/A converter 5 is coupled via anamplifier 6 to aloudspeaker 7. If the input is derived from a digital audio signal source, e.g. a digital audio taperecorder (DAT), it will be fed directly to theDSP 3 with no use of the A/D converter 2. - The arrangement of the DSP 3 is also portrayed in Fig. 3. A digital signal from the A/
D converter 2 is supplied to aninput interface 13 of theDSP 3. Theinput interface 13 is coupled to adata bus 14 which is connected to adata memory 12 for temporary storage of a series of signal data and to one of the two inputs of amultiplier 15. The other input of themultiplier 15 is coupled to abuffer memory 16 for holding coefficient data. Thebuffer memory 16 is coupled at the other end to acoefficient RAM 17 which carries a multiplicity of coefficient data. Upon receiving a timing signal from asequence controller 20, which will be described later, theRAM 17 delivers a corresponding group of the coefficient data in sequence to thebuffer memory 16 where they are retained. Then, the coefficient data are fed to themultiplier 15. An arithmetic logic unit 18 (ALU) is provided for accumulation of numerical outputs from themultiplier 15 and coupled at one of the two inputs with themultiplier 15 and at the other input with thedata bus 14. The output of theALU 18 is coupled to anaccumulator 19 which is connected at output end to thedata bus 14. Thedata bus 14 is also connected with amemory controller circuit 22 which controls data read and write action on an external memory 21 for producing delay data. - The
memory bus 14 is further communicated with anoutput interface 23. A digital audio signal from theoutput interface 23 is then supplied as the output signal of theDSP 3 to the D/A converter 5. - The timing for activating the two
interfaces multiplier 15, thecoefficient RAM 17, theALU 18, theaccumulator 19, and thememory controller circuit 22 is all controlled by thesequence controller 20. Thesequence controller 20 is actuated in accordance with a processing program memorized in aprogram memory 24 and also, in response to an instruction from themicrocomputer 4. Themicrocomputer 4 is coupled with akeyboard 8 for entry of various instructions through key operation. In response to key operations with thekeyboard 8, themicrocomputer 4 controls writing of coefficient data into theRAM 17. - With such a structure, an analog audio signals is converted at each predetermined sampling period into a digital audio signal data which is fed via the
interface 13 to thedata memory 12 for storage. Also, a coefficient data retrieved from theRAM 17 is transferred to thebuffer memory 16 for storage. Thesequence controller 20 provides operational timing for reading data from theinterface 13, for selectively transferring data to themultiplier 15, for retrieving each coefficient data from theRAM 17, for performing multiplication on themultiplier 15, for performing addition on theALU 18, for releasing data from theaccumulator 19, and for delivering calculated results from theinterface 23. Each step of the arithmetic operation, e.g. filter calculation, is triggered by a relevant timing signal. For example, an audio signal data from theinterface 13 is supplied via thedata bus 14 to thedata memory 12 where it is stored. A series of the signal data are then retrieved in sequence from thedata memory 12 and fed to themultiplier 15. Also, coefficient data are in sequence retrieved from theRAM 17 and fed to thebuffer memory 16 for storage. The coefficient data from theRAM 17 are also supplied to themultiplier 15 for multiplication with the signal data from thedata memory 12. Resultant multiplication values are then accumulated with the previous values (held in the accumulator 19) by theALU 18. Subsequently, the resultant sum values are stored in theaccumulator 19. - For production of delay data for application to reflected sound, data from the
data memory 12 is fed via thedata bus 14 to thememory controller circuit 22. Thememory controller circuit 22 writes the supplied data to the external memory 21. After a given length of delay time (for example, τ) elapses, thememory controller circuit 22 reads out the data and releases them as delayed data. The delayed data is then transferred via thedata bus 14 to thedata memory 12 for storage to use in the arithmetic operation mentioned above. - The foregoing arrangement of the DSP 3 is also expressed by an equivalent circuit which is mainly consisted of an
LPF 25 and adigital filter circuit 26 as shown in Fig. 4. TheLPF 25 is constructed in the form of a second IIR filter as illustrated in Fig. 5. TheLPF 25 contains acoefficient multiplier 31 and adelay element 32 both coupled to the input from which an audio data signal is intaken. The output of thedelay element 32 is coupled to another coefficient multiplier 33 and anotherdelay element 34. Also, the output of thedelay element 34 is coupled to afurther coefficient multiplier 35. The outputs of their respective coefficients multipliers 31, 33, and 35 are all coupled to anadder 36. The output of theadder 36 is coupled to adelay element 37. Also, the output of thedelay element 37 is coupled to acoefficient multiplier 38 and anotherdelay element 39. The output of thedelay element 39 is coupled to acoefficient multiplier 40. Then, the outputs of the twocoefficient multipliers adder 36. - Each delay time of the
delay elements multiplier 31 by one sample,and the data to be supplied to themultiplier 35 is a data before the data to be supplied to themultiplier 31 by two samples. This is also the case with themultipliers DSP 3 in accordance with timing signals from thesequence controller 20. The coefficient data assigned to theLPF 25 are retrieved in sequence from theRAM 17 and fed across thebuffer memory 16 to themultiplier 15 of theDSP 3 where they are multiplied by the factor of signal data, which stands for the performance of themultipliers LPF 25. Hence, the frequency characteristics of theLPF 25 are determined by the coefficient data supplied. - The
digital filter circuit 26 may be an IIR filter comprising anadder 41, acoefficient multiplier 42, and adelay element 43, as shown in Fig. 6. An input audio signal is transmitted across theadder 41 directly to the output of thecircuit 26 and also, to thecoefficient multiplier 42. At thecoefficient multiplier 42, the input signal is multiplied by a coefficient -k where k is determined as 0<k<1. An output signal from thecoefficient multiplier 42 is fed to thedelay element 41 where it is delayed by a delay time τ . The delay time τ is equal to 2L/c where L is the distance from a reflection point to a listening point in the narrow room (e.g. between atow board 52 and a listening position P portrayed in Fig. 1) and c is the velocity of sound. The delay time τ is produced by using the external memory 21 in theDSP 3. A resultant output signal of thedelay element 43 is supplied to theadder 41 where it is added to the input audio signal as the original signal. In theDSP 3, themultiplier 42 of thedigital filter circuit 26 is realized by a procedure in which the coefficient data k is retrieved from theRAM 17 and fed across thebuffer memory 16 to themultiplier 15 where it is multiplied by the signal data. - It is assumed that when a pulse signal as an original audio signal A(0) is supplied as shown in Fig. 7-a, a sound B(0) is produced from the
speaker 7 as shown in Fig.7-b and reaches a listening point. The reflected sound B(1) to the sound B(0) also reaches the listening point after time τ elapses. On the other hand, a first compensation signal A(1) is generated in thedigital filter circuit 26 through multiplying the original audio signal A(0) by the coefficient data -k and delaying the result of the multiplication by the time τ . A sound B(1)′ produced from thespeaker 7 by the first compensation signal A(1) is reverse in the phase to the reflected sound B(1), as shown in Fig. 7-c, and will thus offset the reflected sound B(1) at the listening point. However, the sound B(1)′ also develops its reflection B(2) which arrives at the listening point the time τ later. Thefilter circuit 26 again actuates for multiplication of the first compensation signal A(1) by the coefficient data -k and delaying the result of the multiplication by the time τ , producing a second compensation signal A(2). Similarly, a resultant sound B(2)′ from thespeaker 7 triggered by the second compensation signal A(2) is reverse in the phase to the reflected sound B(2) and will thus offset B(2). It is now understood that a reflection B(3) of B(2)′ can also be eliminated by the same manner as described. - The
digital filter circuit 26 may be an FIR filter comprising twodelay elements coefficient multipliers adder 50, as shown in Fig. 8. In this circuit, an input audio signal is fed to thedelay element 46 and theadder 50. An output signal from thedelay element 46 is transferred to thecoefficient multiplier 48 and also, to thedelay element 47 where it is delayed once again. An output signal of thedelay element 47 is fed to thecoefficient multiplier 49. The output signals of theirrespective coefficient multipliers adder 50. - The delay time τ of the
delay elements multiplier 48 is -k₁ and the coefficient of themultiplier 49 is +k₂, on condition that 0<k₁<1 and 0<k₂<1. A low frequency component of the original sound passing theLPF 25 is delayed by τ at thedelay element 46. A delayed signal is then fed to themultiplier 48 where it is multiplied by -k₁ for generating a first compensation signal. Also, the delayed signal from thedelay element 46 is further delayed by τ at thedelay element 47. A 2τ delay signal is then supplied to themultiplier 49 where it is multiplied by k₂ for generating a second compensation signal. Accordingly, theadder 50 receives the first and second compensation signals as well as the low frequency component of the original sound directly transferred from theLPF 25. - In operation, a first compensation signal A(1) is generated in the
digital filter circuit 26 through delaying the original signal A(0) by the time τ and multiplying a delayed signal by -k₁. A resultant sound B(1)′ from thespeaker 7 triggered by the first compensation signal A(1) is reverse in the phase to a reflected sound B(1) and will thus offset the reflection B(1) at the listening point. Also in thefilter circuit 26, the original signal A(0) is delayed by 2τ and a delayed signal is then multiplied by k₂ to a second compensation signal A(2). Similarly, a resultant sound B(2)′ from thespeaker 7 triggered by the second compensation signal A(2) is reverse in the phase to a reflection B(2) and will thus offset B(2) at the listening point. - The foregoing arrangement described with the embodiment is suited but not limited to the processing of one-channel audio signals. Multi-channel audio signals will be processed with equal success using the combination of an LPF and a digital filter circuit for each channel.
- Although the LPF and the filter circuit are controlled for producing compensation signals by the digital operation with the DSP in the described embodiment, they may be arranged in the form of an analog circuit.
- As set forth above, the sound field compensating apparatus of the present invention produces a compensation signal through delaying and amplitude controlling the original signal so that the compensation signal when shifted to a sound wave becomes reverse in the phase to a reflected sound wave and also, a further compensation signal which when shifted to a sound wave, becomes reverse in the phase to the reflected sound of a sound developed by the primary compensation signal. Accordingly, the unwanted reflected sound of the compensation signal sound which is emitted for offsetting the reflected sound of the original sound is successfully eliminated by a further compensation signal and thus, dip in the low range of sound pressure frequencies is diminished at the listening point in a small room where acoustic characteristic will in turn be enhanced.
Claims (3)
- A sound field compensating apparatus for use in a small room where the reflection sound is generated by a sound from a speaker, comprising;
a compensating means for producing a compensation signal through delaying and amplitude controlling the original sound signal so that a sound wave developed from the compensation signal can be reverse in the phase to the reflected sound of the original sound,
wherein said compensating means is produced another compensation signal so that its sound wave can be reverse in the phase to the reflected sound of the preceding compensating sound. - A sound field compensating apparatus for a small room according to Claim 1, wherein the compensating means has an adder means for adding up said original sound signal and said compensation signal to a composite signal for output.
- A sound field compensating apparatus for a small room according to Claim 1, wherein the compensating means comprises a first delay and multiplying means for delaying and amplitude controlling said original sound signal, a second delay and multiplying means for delaying and amplitude controlling said original sound signal, and an adder means for adding output signals of both said first and second delay and multiplying means to said original sound signal.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2265515A JPH04142899A (en) | 1990-10-03 | 1990-10-03 | Sound field correction device for narrow room |
JP265515/90 | 1990-10-03 |
Publications (1)
Publication Number | Publication Date |
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EP0479410A1 true EP0479410A1 (en) | 1992-04-08 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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EP91303677A Withdrawn EP0479410A1 (en) | 1990-10-03 | 1991-04-24 | Sound field compensating apparatus for a small room |
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EP (1) | EP0479410A1 (en) |
JP (1) | JPH04142899A (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2010213135A (en) * | 2009-03-12 | 2010-09-24 | Kenwood Corp | Sound quality adjusting apparatus |
-
1990
- 1990-10-03 JP JP2265515A patent/JPH04142899A/en active Pending
-
1991
- 1991-04-24 EP EP91303677A patent/EP0479410A1/en not_active Withdrawn
Non-Patent Citations (3)
Title |
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* abstract * * |
PATENT ABSTRACTS OF JAPAN vol. 10, no. 061 (E-387)11 March 1986 & JP-A-60 214 193 ( PIONEER ) 26 October 1985 * |
PATENT ABSTRACTS OF JAPAN vol. 13, no. 216 (E-760)19 May 1989 & JP-A-1 029 093 ( NTT ) 31 January 1989 * |
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JPH04142899A (en) | 1992-05-15 |
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