SE437747B - DIGITAL FILTER - Google Patents

Description

Each step in the step filter requires two addition operations, two multiplication operations and one delay operation. The filter is fed from either a periodic digital source for speech sounds or from a digital random source for non-speech sounds.

The filter coefficients are preferably updated after every few milliseconds while the feed signal is updated at a faster rate.

According to the prior art, a bridge filter network has been realized through a suitable programming of large digital computers. An example of Fortran programming of a computer in connection with speech synthesis purposes has been given in the previously mentioned work "Linear Prediction of Speech". Taking into account the data rate of the feed signal and the large number of arithmetic operations, namely two multiplications and two additions for each step in a multi-stage filter and taking into account that an increase in the number of steps in the filter increases the naturalness of the generated number has fast digital computers have been used in most speech synthesis work performed so far. However, Dr. J.G. Dunn, J.R. Cowan and A.J. Russo at the ITT Defense Communications Division in Nutley, New Jersey, tried to implement a multi-stage filter using large-scale integration technology with the metal oxide silicon process (MOS). They intended to use a multiprocessing method in which many arithmetic units were in operation at the same time, but this method requires a large number of multiplier and addition circuits realized on a semiconductor wafer. A discussion of the work of Dr. Dunn and his staff has been published in an article entitled: "Progress in the Development of Digital Vocoder Employing an Itakura Adaptive Predictor" has been published in "Telecommunications Conference Records, IEEE Publ. No. 73" ( 1973). Replacing a bridge structure with different adders and multipliers results in a semiconductor wafer that is large and intricate.

An object of the present invention is therefore to realize a bridge-type filter for generating complex waveforms, for example human speech, on a single semiconductor adhesive. Another object of the invention is to realize the filter components by means of MOS devices. Yet another object of the invention is to obtain a resulting MOS filter of smaller size than is hitherto known in the prior art.

The foregoing objects have been achieved as will be described. The digital filter includes a multiplier, where one input receives the filter coefficients from a memory. The output of the multiplier is applied to an input of an adder-subtractor, the output of which is applied to a circuit which causes a short delay - a short delay circuit. The output signal from the short delay circuit is applied to a circuit which causes a long delay - a long delay circuit. The short and long delay circuits preferably comprise shift registers with respective lengths which are short and long. The output signal from the long delay circuit is connected via a switch to a latch memory. The second input of the multiplier is selectively connected to the output of the adder-subtractor, to the output of the card delay circuit or to the output of the latch memory. The second input of the adder-subtractor is selectively connected to the output of the latch memory, to the output of the long delay circuit or to the output of the adder-subtractor. The multiplier is preferably a group multiplier. The filter output is provided at the output of the latch memory and the input is either connected to the adder-subtractor or to the multiplier in the two embodiments shown.

The nine features which are characteristic of the invention have been set forth in the appended claims. The invention itself, as well as a preferred mode of use and further objects and features thereof, will be best understood by reference to the following detailed description of illustrated embodiments thereof taken in conjunction with the accompanying drawings, in which: FIG. a block diagram showing the basic elements of a speech synthesizer, Fig. 1b shows the presence of the feed signal and the Kn coefficients indicated in relation to the time, Figs. 2a and 2b show a typical bridge filter of the type used in speech synthesizing circuits, Fig. 3 shows a time arrangement for generating the intermediate result in a bridge filter with N steps, Fig. 4 shows a time arrangement for generating the intermediate result in a bridge filter with ten steps, Fig. 5 shows an embodiment of a digital filter equivalent to a bridge filter, Fig. 6 illustrates the various intermediate results available in the filter shown in Fig. 5 at different times within a cycle, Fig. 7 shows another embodiment of a digital filter equivalent to a bridge filter, Fig. 8 illustrates the different intermediate results available in the filter shown in Fig. 7 at different times within a cycle. a cycle, Fig. 9 shows the group multiplier used in the equivalent digital filter, Figs. 10a - 10d show logic diagrams for the different elements according to Fig. 9 and Fig. 11 shows a generalized embodiment of the digital filter.

Fig. 1a shows in block form the basic elements of a speech synthesizer. The speech synthesizer circuit comprises a multi-stage bridge filter 10, which digitally filters a feed signal 11 using filter coefficients Kl-Kn. The bridge filter 10 emits as a signal a digital signal 12, which is converted to analog form by means of a digital-to-analog converter 13. The output signal from the converter 13 is changed to soundable through a speaker 14 or some other suitable conversion device, and it is clear that an amplifier can is applied between the converter 13 and the speaker 1% to amplify the analog output signal from the converter 13 to the levels required by the speaker 14. The feed signal 11, also referred to as "U", is generally derived from one of two sources, namely the speech source here or the source 16 which is not of a speech nature and is also referred to as non-speech. the speech source 16. The particular source to be used is determined by a digital switch 17.

The speech source 15 is used for generating such sounds for which human vocal cords vibrate during speech, for example such a sound as I in Inga. The rate at which the vocal cords open and close determines the pitch of the generated sound.

The non-speech source designated 16 is used in the generation of sounds such as F in Pisces, where the vocal cords are kept open and air is forced past them to the pharynx. Which of the sources 15 and 16 is used depends on which sound is to be generated.

Typically, the non-speech source 16 generates a digital random signal while the speech source 15 generates a periodic digital signal. The digital data provided by sources 15 and 16 can of course simply be stored in one or more semiconductor memories for exclusive readout (ROM memories). Preferably, however, such data is stored in coded form, i.e. as a pitch or as a code that puts a random number generator into operation. Such data is therefore usually decoded before random or periodic data (for example the signal "V") is fed to the filter 10. It is a given that depending on how such data is stored, the need for the switch 17 can be eliminated. When data is stored as a pitch or as a code that activates a random number generator, a gain factor A is preferably also stored in the ROM. The gain A sets the constant amplitude signal "V" from the speech source 15 or the non-speech source 16 to provide a supply signal "V" for the filter 10.

The feed signal 11, which generally corresponds to or mimics the function of the vocal cords, is changed by the bridge filter 10.

The bridge filter 10 generally corresponds to or mimics the function of the vocal range that filters the sound generated by the vocal cords. The filter coefficients Kl-Kn reflect the shape (ie the resonances) of the vocal range during speech. Consequently, the coefficients K1-K2 are periodically updated to reflect the changed shape of the vocal range and can be stored together with data from the speech source and the non-speech source in a read-only memory.

Fig. 1 graphically shows the output signals from the non-speech source 16 and the speech source 15 as functions of time. Shown here is the speech source 15 emitting a pulse every five milliseconds, and this corresponds to a frequency of 200 Hz. This pitch corresponds to speech sounds in many women's vocal range. Because men typically have a lower pitch, a speech source for a man would emit pulses less often. The number source 15 is shown emitting pulses with a period corresponding to the person's pitch, but it is a given that the periodic pulses can be replaced with other periodic functions, for example a decreasing sine wave or the so-called "chirping function", which again starts with a period associated with the pitch. The non-speech source 16 is displayed as a random signal.

The coefficients of the bridge filter are shown to be updated every five milliseconds in Fig. 1b. However, it is clear that the speed at which the 10 coefficients of a bridge filter are updated is a matter of choice in the design.

If the coefficients are updated more often, the bridge filter will better model the dynamics of the volcanic area, but with a corresponding increase in the amount of data to be stored in the mentioned ROM memory. However, it has been found that by updating the coefficients approximately every five milliseconds, a synthesis of very high quality human speech is obtained by means of the bridge filter 10 under reasonable data storage requirements.

The time axis in Fig. 1b is shown divided into intervals of 100 microseconds each. These intervals correspond to the data rate from the speech source 15 and the non-speech source 16 as well as to the data rate to and from the bridge filter 10. Furthermore, it should be noted that although the non-speech source 16 and the speech source 15 appears to be the login signal in Fig. 1b, it is clear that they are in fact digital signals, the magnitudes of which are shown and which are updated at the intervals shown - pooR QUN- * ï-'fï 10 15 20 25 30 According to the time axis in Fig. 1b. For information regarding the derivation of the filter coefficient sizes, reference is made to the already mentioned work "Linear Prediction of Speech".

Therefore, in this embodiment, the data rate of the converter 13 would be 10 kHz, and the upper frequency limit for synthesized speech from the converter 13 would be 5 kHz. It is a given that the data rate can be changed, if desired, by selection in the design. Thus, for example, a data rate of 8 kHz would result in a synthesizer having an upper frequency limit of U kHz.

Figs. 2a and 2b show a block diagram of the bridge filter 10. Fig. Za shows the bridge filter 10 comprising ten steps, S1-S10, and each of these steps is equivalent to the step shown in Fig. 2b. For the sake of clarity, only three of the steps have been shown in detail in Fig. 2a. The input signal to step S10 is constituted by the supply signal 11 and the output signal 12 from step S1 is applied to the converter 13 (Fig. 1a). It is clear to a person skilled in the art that the output signal 27 from step S10 is not used and therefore the adder 27a and the multiplier 27b can be excluded in this step, if desired.

Fig. 2b shows a single step Sn in the bridge filter 10.

An input signal to this step, Yn + 1 (i), is applied as an input signal to an adder 26, the output signal of which is Yn (í). The second input signal to the adder 26, which is applied to a subtraction input of the adder 26, is derived from the output of a multiplier 19, which multiplies the coefficient Kn by the output signal from a delay circuit 22, and this output signal is bn (i- 1). The output signal from the delay circuit 22 is also applied to an adder 21, which also as an input signal receives the output signal from a multiplier 20. The multiplier 20 multiplies the coefficient Kn by the output signal from the adder 26, and this output signal is of course Yn (i). The output of adder 21 is bn + 1 (i). As can be seen, the index of Y and b data indicates the step in which said data is used, while the number appearing in parentheses indicates the cycle within which said data is generated. The delay circuit 22 provides a delay function with a time cycle, and such can be obtained by shift register. Thus, once each time cycle, a new data point U (i) (or Y11 (i)) is provided for step S10 as the feed signal 11. Thus, for each step in the bridge filter 10, two multiplications and two additions must be performed during each cycle, and at the data rates as shown in Fig. 1b, these four operations must take place within 100 microseconds in each step of the bridge filter 10. According to the chosen construction, the bridge filter 10 is shown in Fig. 2a as trained with ten steps, but for a person skilled in the art it is clear that the number of steps can is varied as desired by the construction in accordance with the sound quality desired to be synthesized by means of the bridge filter 10. It has been found that the bridge filter 10 can synthesize in ten steps numbers which in reality cannot be distinguished from real human speech.

It is clear that during a given time cycle, the ten-stage bridged filter 10 must perform twenty multiplications and twenty addition-subtraction operations.

It is further clear that these operations cannot all take place at the same time, this all the more so as V10 must be calculated before Y9, which in turn must be calculated before Y8, etc., during any given time cycle. During the same time cycle, data b -bl 10 must also be used in each step for the next time cycle. The Y-: ch are calculated and stored in the delay circuits 22 (b) data given for Fig. 2b are also shown for steps S1, S9 and S19, different Y and b data being given in the table at the end of the writing). It is clear that the Y and b data as well as the coefficients Kn are multi-digit numbers and that the coefficients K1'K1o and minus one and are updated periodically in the manner shown in Fig. 2a. Equations that indicate relationships between them (see at be- can vary between a decimal equivalent to plus to be described.

Fig. 3 shows a representative form of different spaces obtained from multipliers and adders in bridge filters with n steps. The horizontal axis indicates time and the vertical axis indicates the different steps L a bridge filter 10 with n_ steps. In the nzte step, for example, intermediate results -Kn.bn and Kn.Yn are shown, which can be generated by resp. multipliers 003 Qllählïff Kve- 1U 15 20 30 7806380-7 9 19 and 20 (fig. 2b) and intermediate results Yn and bn + 1 as can (fig. 2b). In terms of time, the intermediate result -Kn.bn must be generated before Yn can be obtained from resp. adders 26 and 21 are obtained, and Yn must be generated before Kn.Yn can be generated, and Kn.Yn must be generated before bn + 1 can be generated. According to the time scale shown, addition operations are required to require a time period of five microseconds while multiplication operations take longer. Regarding the relationship between the generation of the intermediate results in the different steps, it appears that the output signal bn from an addition operation must be available before the multiplication operation -Kn.bn is started, and this is indicated by the arrow 25. This condition necessitates that a period 23, which indicates "no operation", is inserted between the addition operation bn + 1 and the multiplication operation -Kn.bn, if only one addition operation and a multiplication operation are to be initiated for an arbitrary given time period of five microseconds, as shown in Fig. 3.

Periods Zü of the "no operation" type are inserted after the second addition operation before the following multiplication operation for symmetry purposes. It is thus clear that the operations specified in all the steps of a bridge filter against n steps can be combined in the order indicated in Fig. 3 and the intermediate results in question become available as required. Fig. 3 indicates the general nature and applicability of the digital implementation in a multi-stage bridge filter which will be described. It is clear that the representation in Fig. 3 shows the operations performed during one of the already mentioned time cycles. The time period of five microseconds for an addition operation has been chosen as the starting point for the design due to the compatibility with P-channel MOS-type integrated circuits. However, it is a given that other time periods may also be used if desired.

Pig. Fig. 4 shows a representation which is of a similar kind to the device shown in Fig. 3, but the repositioning in Fig. H is a digital realization of an equivalent bridge filter 10 with ten steps and the horizontal time axis has been increased. to display more than one time cycle. Furthermore, the time cycle has been divided into twenty time periods, T1-T20, and each of these preferably has a duration of the order of five microseconds. As already mentioned, other periods can also be selected. Also in Fig. H, the time cycles, i.e. i-1, i and i + 1 have been specified in order to make it easier to compare the availability of intermediate results in the filter 10 with the requirements set by the representation of the filter 10 by mathematical formulas given in Table 1. " the first time period, T1, is applied to the supply data U as an input signal, and the output signal, Y4, from the filter becomes available at the time period T11. A comparison of Fig. H with Table I shows that the different input signals required for multiplication operations are available when they are required and that the different inputs for the addition operations are also available when required.For, U further shows that an addition operation (which preferably requires a time period) is initiated and completed each time period and that a multiplication operation is similarly initiated ( and completed) each time period even though the particular multiplication operation then initiated is not completed in eight time periods. The apparatus for performing these operations will be described in detail in connection with Figs. 5, 9 and lüa-d.

It has been mentioned that a multiplication and an addition operation are each preferably initiated each time period. In fact, preferably the number of time periods in a cycle is equal to twice the number of steps in the equivalent bridge filter. Thus, for bridge filters with eight or twelve stages, the equivalent digital filter preferably has sixteen or twenty-four time periods per cycle. It is clear from Figures 3 and 4 that the number of time periods allocated for the multiplication operation depends in part on the number of time periods in a cycle. Thus, eight time periods can be used for multiplication operations in an equivalent digital filter with ten steps, while six time periods can be used for multiplication operations in an equivalent digital filter 10 15 20 25 30 7806380-7 11 filter with eight steps, if the digital equivalent filter scheme in Fig. 3 and H is followed. It is clear to a person skilled in the art that the number of time periods for the multiplication operation tends to dictate the number of bits that can be multiplied, ie. tend to limit the number of bits used to represent the Kn coefficients. In most applications, the number of bits assigned to the Kn coefficients by following the processing scheme of Figs. 3 and H will result in a somewhat acceptable synthesized number. However, if even greater accuracy is desired in the representation of the Kn coefficients, a multiplication and an addition operation are not questioned every time period in a cycle and a certain delay is introduced at a point during the cycle. It is a given that the cycle will then require a longer time to be completed and thereby the data speed (and frequency reproduction) in the plant will be reduced. As shown in Fig. 4, the intermediate results K1Û.Y10 can be obtained or obtained, but as already mentioned in connection with Fig. 2a, these special intermediate results are not required for a digital realization of the bridge filter. However, Fig. 5 shows that the intermediate results K1Ü.Y10 and become (or some other numbers) are often lältarc all generate (and ignore) than it is to prevent the apparatus from making these calculations. It will be further described later how the multiplication operation performed by the multiplier 18 (Fig. 1) can be effected instead of the calculation of K10.Y10 through the apparatus.

Fig. 5 shows a block diagram for a digital realization of an equivalent bridge filter 10. The filter includes a group multiplier 30, adds the subtractor circuit 33, a delay circuit 34 for a period, a shift register 35 and a latch memory. 36. The data entered into and output from these different units at each of the twenty time periods T1-T20 (for an equivalent bridge filter with ten steps) are given in list form in Fig. 6. Referring to Figs. 5 and 6, it can be seen that the group multiplier 30 produces the multiplications performed by the multipliers Pècfft Oz: i ALIry 7806380-7 CP 10 15 20 25 30 12 19 and 20 (Figs. 2a and Zb) in each of the steps of the bridge filter. The group multiplier that is stored in the K-bar receives 31 Yq or bn data via the cable H0. the coefficients Kl-Kln via conductor 32 and either the K-bar 31 preferably comprise ten shift registers, each of which is ten steps.

The data stored in the K-bar 31 are given in Table II and fed to the group multiplier 30 via conductor 32. The group multiplier 30 initiates a different multiplication operation each time period (as indicated in Fig. H), i.e. approximately every fifth microsecond. As shown in Fig. 9, the group multiplier 30 preferably has eight steps, and a series of addition and shift operations are performed as the data progresses through its eight steps and the data is multiplied by the relevant K coefficient stored in the K-bar 31. Multiplication operations requires 40 microseconds but since a new multiplication operation is initiated every five microseconds, eight multiplications are in different completion stages at a given time. The calculation period of eight time periods shown by the group multiplier 30 can be seen in relation to the multiplication inputs and outputs indicated in Fig. 6. By way of example, the inputs fed to the multiplier at the time period T1 are output from the multiplier eight time periods later at time period T9. The coefficients stored in the K-bar 31 are stored sonnet numbers consisting of nine bits plus an additional bit for character information. As already mentioned, these nine-bit numbers range from -1 to +1 (decimal equivalents) and it will be shown that the structure of the group multiplier 30 is thereby simplified.

The output signal from the group multiplier 30 is applied to the addition subtraction circuit 33. In the preferred embodiment, this output signal is a channel consisting of thirteen bits in parallel, namely twelve data bits and one bit for sign information. It is clear to a person skilled in the art that the number of bits in the data channel is a design choice. The second input signal to the addition subtraction circuit is obtained from the (1) supply signal 11 at the time period T1, the output signal from the addition subtraction circuit 33 during the time periods T2-T10, the output signal from the shift register 35 during the time periods T11-T19 and the output signal from the latch memory 36 at the time period T20. The particular input signal to the addition subtraction circuit 33 is shown for simplicity as controlled by various single-pole one-way switches 37A-37D, but it is clear that semiconductor switches can be used to advantage to perform these switching functions as well as the other specified switching functions. The output of the addition-subtraction circuit 33 is applied to the switch 37B, the switch 38A and the Sgm an input signal to a delay circuit 3H for a period of time. The output signal from the addition subtraction circuit 33 also consists of a channel with a width of thirteen parallel bits which is delayed by a period of time in the circuit 34 before being applied as an input signal to the shift register 35 and to the switch 38B.

The shift register 35 stores data from the thirteen bit wide channel in thirteen shift registers, each having eight steps. The shift register 35 is arranged to perform the shift operation only during the time periods T12-T2. The output signal from the shift register 35 is fed to the switch 37C and the switch 39. The switch 39 is closed at the time period T20 to control the output signal from the filter, Y1, into the latch memory 36. The output signal 12 from the latch memory 36 is fed to the digital-to-analog converter 13 (fig. la) and to switches 37D and 38C.

Switch 37B closes during time periods T2-T10, switch 37C closes during time periods T11-T19 and switch 37D closes during time period TZÜ. Switch 38A closes during time periods T13-T1, switch 38B closes between time periods T3-T12 and switch 38C closes during time period T2. The other sides of the switches 38A, 38B and 38C are connected to the input of the group multiplier 30 via the cable 40. In Fig. 6 the different intermediate results appearing in the circuit shown in Fig. 5 during the time periods T1-T20 have been listed. Referring to Fig. 6, it can be seen that one of the inputs to the multiplier consists of information for the Kn coefficient during the that the second input signal varies according to which of the switches 38A-380 is closed In the time period T1, the switch 38A is closed, as already indicated, and the output signal from the addition subtraction circuit 33 is in this case b2 (i-1), and the is applied as an input signal to the multiplier, at the same time the second input signal to the adder is the supply signal (U (i).

At the time period T2, the second input signal to the multiplier b1 (i-1) and this, according to Fig. 5, comes from the output of the latch memory 36 via the switch 38C. The output signal from the latch memory 36 is then according to Fig. 6 Y1 (i-1), but remembering the last entry in Table I, it should be remembered that b1 (i-1) is set equal to a delayed signal Y1 (i), i.e. Y1 (i-1). At the time period T2, the second input signal to the adder is the one emitted at the same time at the output of the adder, namely in this case Y1U (i). At the time period T3, the input signals to the multiplier are K10 and Y10 (i) which are derived from the output of the circuit 34, which is delayed by a time period. It is given that the results of this multiplication are not available until at time period T11, and at this time they will be provided as one of the inputs to the addition subtraction circuit 33. At time period T11, the second input to the addition subtraction circuit 33 will be taken from the output of the shift register 35. The first term entered from the shift register 35 is the term b1O (i-1), which is first issued from the shift register at time period T2 and remains at the output of the shift register, since the shift register 35, as already mentioned, does not shift between time periods T3 and T11. At the time period T13, the input signal to the group multiplier 30 will again be obtained from the output of the addition subtraction circuit 33 via the switch 38A. At time period T20, the term V1 (i) will be output to the latch memory 36 from the shift register 35 and the instantaneous output signal from the latch memory 36, namely Y1 (i-1) will be applied to the second input of the addition subtraction circuit 33 via the switch 37D to provide the term b1 (i-1), as already indicated. 10 15 20 25 30 7806380-7 15 The latch memory 36 stores the filter output signal (Yi) during a cycle.

The block diagram according to Fig. 5 has already been explained previously. The filter according to Fig. 5 can also be used in an application equivalent to an N-stage filter with a M-stage multiplier (ie there may be m + 2 bits in the Kn coefficients), if a shift register with a delay equivalent to NM-2 time periods are introduced between the addition subtraction circuit 33 and the circuit 3H which is delayed by a time period. The connection to the switch 38A then takes place from the output of the added shift register and the delay associated with the shift register 35 must then be set equal to N + M-1. This generalized embodiment of the digital filter is shown in Fig. 11. In the embodiment shown in Fig. 5, NM-2 is equal to zero and therefore no delay is required in this embodiment. In the embodiment described in connection with Figs. 5 and 6 is N + M-1 equal to seventeen, which reflects the number of time periods that exist between the time for data entry on the shift register 35 and the time when data leaves the shift register 35.

For example, according to Fig. 6 b2 (i-1), data is entered in the shift register 35 at the time period T2 and leaves the shift register 35 at the time period T19, seventeen periods later. However, the shift register 35 has only eight steps in this embodiment and the additional delay during periods T3-T11 is obtained by not shifting the shift register 35. These nine periods correspond to the time when Y2-Y10 data are available on the 3% output of the one-period delay circuit, which data do not need to be entered on the shift register 35, as shown in Fig. 6.

The number of steps in the shift register 35 plus the possible number of time periods per cycle that data is not shifted within the shift register 35 is equal to the time period delay N + M-1 through the shift register 35.

It can be seen that the equivalent ten-stage bridge filter according to Figs. 5 and 6 performs the filtering operation required at the bridge filter 10 in Fig. 1a at reasonable data rates. In the preferred embodiment, for example, feed data 11 is applied at a rate of 10 kHz (i.e., every 100 microhah.

T \ ånwíi 'J; W »uÄ, Ä 10 20 25 iso 7806380-7- 16 seconds) and the basic addition operations in the addition subtraction circuit 33 as well as in the group multiplier 30 and the shift operations in the circuit 34 which delays by a time period and in the shift register 35 takes place within time periods which nominally amount to to five microseconds. It is clear to a person skilled in the art that such speeds are well within the speed range for large-scale MOS-type integration devices with a P-channel design, and the filter shown in Fig. 5 can be incorporated into a relatively inexpensive P-channel type MOS LSI semiconductor wafer. for speech synthesis or generation of complex waveforms. It should also be clear to a person skilled in the art that the basic arrangement of the equivalent step filter with ten steps in Fig. 5 is also applied to digital filters which are equivalent to bridge filters with other number of steps. Ten steps have been chosen in the preferred embodiment of the filter because ten-step bridge filters for linear prediction coding of speech synthesizing circuits have been selected as standard for use in the United States Department of Defense. If one wishes to practice the invention would like to utilize a digital bridge filter with a different number of equivalent steps, it is to be noted that the number of time periods into which a cycle is divided must be at least equal to the number of equivalent steps. In the preferred embodiment, the number of time periods (twenty) is equal to twice the number of equivalent steps (ten). For example, if one were to wish to use a filter equivalent to twelve steps, the number of time periods per cycle would amount to at least twenty-four and the basic construction described so far would only need to be extended. It is to be noted that for a digital bridge filter with twelve equivalent steps, the group multiplier included therein could use peak time periods to complete a multiplication of the basic scheme already described, so that an addition and a multiplication operation is initiated every time period. This is shown in Fig. 3 by equating N with twelve and the diagram in Fig. 3 is hereby supplemented accordingly. It is a given that if the period of five microseconds for each time period is maintained, the data rates that can be taken care of by the twelve-step version will be less than for the filter version which has ten steps. It is worth noting that by increasing the delay time through the group multiplier 30, the number of bits in the coefficients K1-K12 can be increased from a total of ten bits to a total of twelve bits.

Similarly, if an equivalent eight-step digital filter were desired, the number of time periods in a cycle would amount to at least sixteen, and by setting N equal to eight in Fig. 3, it would be seen that the travel time through the multiplier 30 would amount to six time periods. In this case, by using the group multiplier which will be described in detail later, the number of bits in the coefficients from the K-bar 31 required would be limited to no more than eight bits. However, as already mentioned in connection with Fig. Håkan, several time periods can be used to effect a multiplication operation in certain embodiments. This may be desirable here as a design choice if further accuracy is desired in terms of the Kn coefficients. The additional accuracy would require several bits in the Kn coefficients and this in turn would require greater delay through the group multiplier 30. The basic construction in the case of equivalent filters according to Fig. 5 would be modified to some extent due to the fact that then a multiplication and an addition operation would not be initiated every time period.

It is clear to a person skilled in the art that in this case some of the intermediate results obtained within the filter would need to be stored temporarily and this would require that additional storage elements be included in the filter according to Fig. B. Although such modifications have not been specified in detail, such a modification in terms of the digital implementation of bridge filters would be within the scope of possibility for a designer of digital circuits.

It has been previously mentioned that the intermediate results K1U.Y10 (i) and b11 (i) are generated by the digital filter according to Fig. 5, but that these intermediate results are not used because PÛÛR 10; ._ \ cs '20 25 30 35 7806380-7 _ 18 they are not required to implement bridge filter 10 according to Fig. 1a. Recalling that data (V) from the speech source or (A) through a multiplier 18 in the conventional speech synthetics non-speech source is multiplied by a gain factor circuit in Fig. 1a, it has been found that this multiplication can take place through the group multiplier 30. during the time when Km An embodiment of the digital filter performing this multiplication (V (i) .A is shown in Fig. 7. intermediate results generated by the circuit shown in Fig. 7.

If one briefly refers to Figs. 7 and 8, it will be seen that this circuit (including the intermediate results generated .Y10 (i) would otherwise be generated by the group multiplier.

Fig. 8 shows the differences thereof) similar to the circuit shown in Fig. 5 with the following modifications. The identification numbers in Fig. 7 are largely the same as those used in Fig. 5 but have been given a prime character (') added for easier identification. The data (V) to be amplified by the gain factor A is applied to an input of the group multiplier 30 'via a switch 38D' at the time period T3 instead of applying the output signal from the delay circuit 34 at this time. At the time period T11, when the multiplication has been completed to form U (i + 1) i.e. OFF (i + 1), logic zeros are input to the second input of the addition subtraction circuit 33 'instead of an entry of b10 (i-1) into data from the shift register 35. It is further given that both the Kn coefficient data and A gain data must be entered in the K-bar 31 '. As can be seen from Figs. 7 and 8, this embodiment has the function performed by the multiplier 18 (Fig. 1a) incorporated with the digital realization of the bridge filter 10. The data stored in the K-bar 31 'have been given in the table. III. The gain factor A is preferably updated at the same rate as the K-n coefficients are updated in the K-bar 31 '.

In Fig. 9, the block multiplier 30 is shown in a block diagram. Leaders 32-1 up to and including 32-9 receives the least significant t.o.m. the most significant bit in the coefficient data from the K-bar 32. On conductor 32-10, sign data is received from the K-bar 32. Another input signal to the group multiplier vooao 10 15 20 25 30 35 ..._-___.__- .. __.._ a-. _ _ 7806380-7 19 30 received via cable 40. Conductors 40-1 t.o.m. 40-12 in cable 40 carries the least significant t.o.m. the most significant bit and conductor 40-13 carries the sign for data on cable 40.

In Fig. 9 there is a group of elements with the reference letters A, B, C or D (elements without a reference letter are also elements of "A" type and also correspond to Fig. 10a). These 'elements A-D correspond to resp. circuits 10a-10d. With brief reference to Figs. 10a-10d, the circuits shown therein are enclosed within dashed lines, with some conductors extending beyond the dashed line. The relative position of the conductors crossing the dashed line in Figs. 10a-10d corresponds in position to the conductors making contact with elements A-D in Fig. 9. In Fig. 9, the elements are arranged in eight rows and twelve columns. The eight rows correspond to the eight previously mentioned steps in the group multiplier 30. These steps have been identified on the right side in Fig. 9 and include the eight shift register cells 51 which are connected to conductors 40-13. The twelve columns correspond to the twelve bits of numerical data (on conductors 40-1 through 40-12) that come as input signals to the group multiplier 30. Data on conductors 40-1 through. 40-13 go through the group multiplier 30 step by step in shift registers at the multiplication in the group multiplier 30.

The thread time through a given step is thus of the order of the previously mentioned forward microseconds or thereabouts.

The conductor 32-1 from the K-stack 31 is connected to an input of twelve AND gates 52-1 up to and including 52-12 and the second input on each gate is connected to res. leader 40-1 t.o.m. 40-12. The output signals from AND gates 52-12 up to and including 51-1 is applied to the partial sum inputs of elements of types A and B in step 1 (see Figs. 10a and 10b).

Leaders 32-2 t.o.m. 32-8 are connected to K-stack inputs for elements of type A (fig. 10a) in resp. steps 1-7 in the group multiplier 30. The conductor 32-9 is connected to the input therefrom in C-type elements in step 8 (see Fig. 10c). The data available on conductors 40-1 up to and including 40-12 are connected to the inputs "data in" on the elements of step 1 and are connected via these to step 2 up to and including step 8 through the "data out" terminals of these elements 10 15 20 25 30 35 7806380-7. The input signal with the partial sum in the element 1 of the stage 1 is derived from the outputs of the AND gates 52-1 up to and including 52-12. In the following steps, the partial sum is derived from the outputs of partial sums from the second most significant bit in the previous step, with the exception of the input signal for partial sums of elements in the position corresponding to the most significant bit, the input signal of which indicating the partial sum derived from the transmission output signal from the position of the most significant bit in the previous step. Otherwise, the connections which output transfer numbers from the elements are connected in series with the elements for entering transfer figures in each step.

Referring to Fig. 10a, it can be seen that data from the K-pillar 31 determines whether the "partial sum" is to be connected directly to the "partial sum" via or transfer gate 60 or to the output of EXCLUSIVE-OR gate 62 via a transfer gate 61 An AND gate 63 and an EXCLUSIVE OR gate 64 respond for data to "data in" and "partial sum". The EXCLUSIVE OR gate 62 responds to the output of the EXCLUSIVE OR gate GH and to the "transfer digit in".

An AND gate 65 responds to the output signal from the EXCLUSIVE OR gate 64 and to the "transfer digit in" and the output signal therefrom is provided together with the output signal from the AND gate 63 on an OR gate 66, the output of which is "transfer digit out" .

"Data out" corresponds to "data in" delayed by a shift register section 67, which for example comprises two inverters. As shown in Fig. 1Ûc, a C-type element is identical to an A-type element, with the exception that no "data out" connection has been provided, nor has a shift register 67 been provided. Fig. 10b shows a B-type element and this provides only a "data out" connection connected to a shift register 67 ', the input of which is "data in" and a connection "transfer digit out" is provided through an AND gate 68 , whose input signals are "data in" and "partial sum in".

I fig. 10d, a type D element produces only a signal "transfer digit out" from an AND gate 68 ', the input signals of which are "data in" and "partial sum in". o. o EoRQÄÉÉYi, 10 20 25 30 35 7806380-7 21 It appears that a new partial sum is calculated at each step, and this includes a necessary transfer of transfer digit information between elements in a step, but "partial sum out" remains unchanged, if data on the K-stack conductor is a logical zero, or is added to data on the "data in" to provide "partial sum out", if the data on the conductor from the K-stack is a logical one. The partial sums are shifted to subsequent less significant locations as the data is shifted through the group multiplier. It is a given that a smallest significant bit is lost in each step of the group multiplier. However, the Kn coefficient data from the K-bar 31 corresponds to a number within the decimal range -1 to +1 will, if logic zeros appear on the conductors 32-1 up to and including 32-9, the output of the group multiplier 30 will be a logic zero, and vice versa, if the data on the conductors 32-1 up to and including 32-9 are all logical ones, the data input to the cable 40 to exit the bounce multiplier 30 is unchanged. For other possible data patterns on conductors 32-1 through 32-9, data on cable H0 will be scaled between zero and the value entered on cable 40 during 29 possible steps according to the size of the data on conductors 32-1 through. 32-9.

As the data is shifted through the group multiplier 30 step by step in shift registers, data from the K-bar 31 will be skewed as shown in Tables II and III to ensure, for example, that the relevant bit in the relevant coefficient arrives at the relevant time in the group multiplier 30. In FIG. 10a-10c, the time pulses for activating these circuits on the said shift register display have not been shown, since this is well known by specialist timing functions can be achieved in Figs. 10a-10c shown by the man, but such by adding clock gates to the 1 circuits or by using logic that is pre-charged or has arbitrary discharge, and therefore such timing devices have not been shown in detail.

According to Fig. 9, the list data on conductors H0-13 will only be delayed during the eight-step delay or in the group multiplier 30 via shift register element 51 and compared. i PÛOJ; QUÄIJ J (11 10 15 20 78-06380-'7 22 then with list data from the K-bar 31 on the conductor 32-10 at the EXCLUSIVE OR gate 53, thereby providing the correct sign for outgoing data according to the normal rules of multiplication.

The group multiplier 39 (or 30 ') shown in Figs. 5 and 7 has been described in detail. The remaining elements, for example the addition subtraction circuit 33 (or 33 '), the period delay circuit 34 (or 3H'), the shift register 35 (or 35 ') and the latch memory 36 (or 36') are not shown in detail, since cool conventional elements are well known.

The addition subtraction circuit 33 (or 33 ') receives data with signs of its two inputs and must determine whether a subtraction or an addition operation is requested or based on the particular sign entered with the data. Since the invention has now been described with respect to several embodiments thereof, additional modifications will be apparent to one skilled in the art. The invention is not limited to the particular embodiments described but only by the claims. ågon QUALITY! 9: a I'IK'IA'I'IIJ! * E 23 TABLE ylo¶i> = xll-xl0bl0 y9 (i) = Yl0 (i) -x9b9 (i-1) bl0 (i) = b9 (i- 1) + K9Y9 (i) I 7806380 ~? z3 (i) = Y9 (i) -K8b8 (i-1) b9-b8 + x8Y8 (i> 27 (i) = y8 (i) -K7b7 (il) b8 (i) = b7 (il) + K7Y7 ( i) Y6 (i) = Y7 (i) -K6b6 (i-1) Y5 (i) = v6 (i) -x5b5 (i-1) b6 (i) = b5 (il) + K5Y5 (i) Y4 ( i> = y5 b4 (i) = b3 (il) + K3Y3 (i) Y2 (i) = Y3 (i) ~ K2b2 (il) b3 (i) = b2 (il) + K2Y2 (i) ¥ lß; 3 = z2-xlbl b2 (i) = bl (il) + KIYl (i) bl (i) = Yl (i) 24 o1e06380'7 omm mm Nm mm mm mm mm mm mm o mm omlNm _ Alu m3. l fl vmvøh omm mm Nm mm mm mm o mm mm mm mm muNm AJ mm omm mm Nm mm mm mm mm mm mm mfNm mm mm omm mm Nm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm m..Nm, mm mm mm mm mm mm mm Nm mm mm TNm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm Nm N..Nm 1 n. mm about mm mm mm mm mm omm mm Nm m..Nm L oN @ mmm mmm mmm mmm mmm mmm mmm Nma mmm omm mm. mm. E. ma mm F ... mm. Nm. mm. 23mm than m fl mmmumm, Iam mmwmlm .mmccnæmmwnnß wbwhwmnmmmw HH .. om .mm fl mäm fi mlww Vmwmß .mmmgmm fi mm .fi wwmmñ HH, 7806380-7 25 m .. 4 ä. N .. m .. f. mv. m .. fm. f. 4 ... Nlßll fi ß, I fi øv. ... f. 4 ä. N .. N .. fm. fffm. ..- Nm Al. n mm. <ä. NV. m .. f. m .. f. f. NV. .TNN ß. W .. m .. 4 ä. N ... m .. fm. Ff .TNN ff N ... m .. 4 H .. N .. N ... fm. F. .LNN m .. w .. J. m ... m .. <N ... N .. N .. N .. fm. .TNN w ... fm. m .. fm. m .. 4 f. N .. m .. f. TNN mn ... ffm. w .. N .. f. N .... .N ä. NV. m .. TNN No. 1.

N .. m .. f. M .. f. F. M .. m .. <ä. N .. N..N. ~ N .. m .. f. M .. f. N .. m .. m .. <ä. NV. ... NN S ... o ... 9 .. N ... E. m ... m ... F ... m .. N ... ä .. Mon .. ... m QoÉ fi mwQHW mmm fi mmmwn ... Pñßwwmwm .. m ... ... ÉNHNJM å ... ... ënëà ... am 4 HHH AA mm 4 H ... fi mmmwwlnm E% Q! Ïn. -r. '~'. "" '* a ~,. ,, ¶ “' L 78Ü638Û-'I zb aa ~ a ma aa ma ma» a ma i Éàlbllmam l fi uxuwm. aa Na ma aa ma ma aa wa mon A ...: f maa aa Na ma .aa ma ma ma ma ma ma fi a aa Na ma ma ma ma Tmm ma ma maa .aa Na ma .aa ma màm .W ma aa ma fa aa Na ma ma màm .m wa ma aa ma ma maa aa Na ma ... àm am ma ma ma ma ma maa aa Na màm m. 1 aa ma ma 7 »a ma. ma fi a f. Twm f m2. mä. Sa. m2. m3. ïa. m3. wä. mšmmåäm momamammaa .amnmaamamnmw ïäuammmmm. m? aaâamam fi a aäma fi e fl wå. m âm mwHH AAmFZH

Claims (7)

10 15 20 25 30 35 7806380-7 2? 1. A digital filter arranged to be actuatable by two different input signals, namely a digital supply signal and a plurality of digital values representing filter coefficients (K) and comprising first memory means (3l; 3l ') for storing said plurality of digital values. , which memory means are connectable via first circuit means (32: 32 ') to a multiplication circuit (30; 30') which is connected to an input of an arithmetic circuit (33: 33 '), and second memory means (34, 35, 36; 34 ', 35', 36 ') for storing data output from the arithmetic circuit, second circuit means (40; 40') being arranged to connect the second memory means to an input of the multiplication circuit, k ' drawn by the other circuit means (40: 40f) are arranged to select 2. Eivt (via 33A, aan, sec; say, 3832 3ec ') buy the output of the arithmetic circuit (33: 33f) to an input of the multiplication circuit (30; 30') in connection with selective connection of the others the outputs of the memory means (34, 35, 36; 34 ', 35f, 36') to an input of the multiplication circuit for obtaining a bridge filter (10), at the output of which a digital output signal filtered depending on the input signals is output. Filter according to claim 1, characterized in that the second memory means (34, 35, 36; 34 ', 35', 36 ') comprise first and second delay circuit means (34 and 35; 34' and 35 '). in the second delay circuit means (35: 35 ') is longer than the delay in the first delay circuit means (34: 34'), and in that the second circuit 40 ') is arranged to selectively (via 383, 38C ;, 38B') , 38C ') connect the first and second delay circuits- i 3o'). A filter according to claim 1 or 2, characterized by a third circuit means (37D, 37C, 37B; 37D ', 37C', 37B ') for selectively coupling the second memory means (34, 35, 36; 34'). , 35 ', 36') and the outputs of the arithmetic circuit (33: 33 ') to an additional input on that arithmetic means (40; the outputs of the multiplication circuit (30; the optical circuit). 10 15 20 25 30 35 7806380-7 3. Z? Filter according to claim 2, characterized in that the second memory means (34, 35, 36: 34'.35 ', 36') 36 ') for temporary storage of data comprise latch memory means (36; provided by the the arithmetic circuit (33; 33 '), the second circuit means (40: 40') being arranged to selectively (via 38C; the ion circuit (30: 30 ') 5. A filter according to claim 4, characterized in that the third circuit means (37D, 37C, 37B; 37D ', 37C', 37B ') are arranged to selectively couple the output of the latch memory means (36: 36'), the other delay circuit means (35; 35 ') and the arithmetic 38C') to the multiplexer means. The outputs of the magnetic circuit (33; 33 ') to a further input of the arithmetic circuit. A filter according to claim 5, characterized in that the second circuit means (40: 40') comprise first switching means (380, 38B). 38A; 38C ', 38B', 38A ') for selectively coupling the latch memory means (36; 36'), the first delay circuit means (34; 34 ') and the arrhythmia the optical circuit (33; 33 ') outputs to an input of the multiplication circuit (30; 30'), and in that the third circuit means (37D, 37C, 378: 37D ', 37C', 37B ') comprise second switching means for selectively coupling the latch memory means (36). 36 '), the outputs of the other delay means (35; 35') and the arithmetic circuit (33; 33 ') to said further input on the arithmetic circuit. 7. characterized in that the supply signal (via II) can be connected to the multiplication circuit (30:30,) by means of the second circuit means (40; 40 '), a gain factor associated with the supply signal being stored in the first A filter according to any one of the preceding claims, the memory means (31: 31 ') together with the digital values. 8. feel that the supply signal is arranged Filter according to one of the preceding claims. to be connected to the arithmetic circuit (33; 33 '). 9. Know that each of the digital values A filter according to any one of the preceding claims, which is arranged to be updated once every several cycles 780-6380-'7 7.-'1 while the supply signal (via ll) is arranged to be updated during each cycle, each cycle including a plurality of time periods (T) and the multiplication circuit (30: 30 ') is arranged to start a new multiplication operation at each time period and to require a plurality of time periods to complete a multiplication operation. 10. a feature of means (13, 14) connected to a filter according to any one of the preceding claims, the arithmetic circuit (33; 33 ') for obtaining selected outputs therefrom and arranged to convert these selected outputs into synthesized human audio signals.