CH633922A5 - Digital filter and use thereof in a voice-synthesis device - Google Patents

Description

The present invention relates to a digital filter operating in response to a digital excitation signal and to a plurality of digital values representing filter coefficients, comprising a first memory for storing a plurality of said digital values, a multiplier circuit, first means for coupling said first memory and said multiplier circuit, an arithmetic circuit having an input coupled to said multiplier circuit, a second memory for storing the information leaving said arithmetic circuit and second means for coupling output information from said second memory at an input of said multiplier circuit. 30 Different methods have been commonly used and tested with regard to the digitization of the human voice and its synthesis from digital signals.

For example, pulse code modulation (PCM), differential pulse code modulation, adaptive predictive coding, delta modulation, “Vocoders” channels, “Vocoders cepstrum”, “Vocoder to formants ”,“ Voice-excited Vocoders ”, as well as linear predictive coding methods for speech digitization. These methods are briefly explained in the article "Voice signais: 40 bit by bit" on pages 28 to 34 in the October 1973 issue of "IEEE Spectrum".

Computer simulations of different speech digitization methods have generally shown that linear predictive speech digitization methods can produce speech reproducing speech with more naturalness than previously known "Vocoder" systems (eg Vocoders channels) and this with a lower data rate than that of pulse code modulation systems. As will be seen, the linear predictive system 50 can advantageously make use of a multi-stage digital filter, and the timbre of the resulting speech generated is all the more natural the higher the number of stages of the digital filter.

The first applications of linear predictive methods for digital speech synthesis took place at the earliest in the 1960s and at the latest in the 1970s. A historical analysis of some of these preliminary works is presented in the article by Markel and Gray, "Linear Prediction of Speech" (Springer edition, New York, 1976), 60 pages 18-20.

The multi-stage digital filter used in linear predictive coding is preferably an “all pole” filter, all of whose roots preferably intervene inside the unitary circle Izl = 1, the mathematical transfer function of the filter 65 being expressed. as "transform Z". The filter itself can take the form of a grid filter of the type shown in Figs. 2a and 2b; however, other filters, and in particular mesh filters and standard mesh filters, as well as

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other types of filters are also known for such use, as indicated in chapter 5 of the article “Linear Prediction of Speech”. As will be seen, each stage of the grid filter requires two addition operations, two multiplication operations and one delay operation. The filter is excited either by a periodic digital source for voice sounds, or by a random digital source for sounds other than voice sounds. The filter coefficients are preferably readjusted every few milliseconds, while the excitation signal is readapted at a faster rate. 10

In the prior art, a grid filter network has been produced by appropriate programming of large digital computers. The "Fortran" programming of a computer, intended for speech synthesis, was for example presented in the previously mentioned article "Linear Prediction of Speech". Given the data rate of the excitation signal and the large number of arithmetic operations, namely two multiplications and two additions for each stage of the multi-stage filter, and given that an increase in the number of stages of this filter improves the naturalness of the generated speech, extremely fast digital computers have been used in most of the speech synthesis tests carried out to date. However, Dr. J.G. Dunn and MM. J.R. Cowan and AJ. Russo, of ITT's defense communications division, in Nutley, New Yersey, tried to make a multistage filter using large-scale MOS integrated circuit techniques. They attempted an approach using multiple processing, in which many arithmetic units were operated simultaneously; however, this technique requires that a very large number of 30 multiplier and adder circuits be established on a semiconductor wafer. Some considerations regarding the work of Dr. Dunn and his teammates are set out in an article entitled "Progress in the Development of Digital Vocoder Employing an Itakura Adaptive Predictor", published 35 in "Telecommunications Conference Records, IEEE, no 73" (1973) . The replacement of the grid structure by numerous adders and multipliers results in a very complex and large integrated circuit semiconductor wafer. 4o

As a document illustrating the prior art, mention should also be made of the US patent disclosures Nos. 3,662,115,

3,908,085.3,975,587.4,022,974.4,052,563.4,058,676.

The object of the present invention is to provide a digital filter particularly well suited to the generation of complex waveforms, such as that of human speech.

According to the invention, this object is achieved by the presence of the characters set out in the first claim.

The dependent claims define particularly advantageous embodiments. 50

Note that embodiments of the digital filter allow it to be produced on a single semiconductor wafer.

Furthermore, in certain advantageous embodiments, the components of the filter are produced using MOS elements. In this case, it is possible to obtain an MOS filter of dimensions 55 smaller than those which were known in the prior art.

According to its general principle, the digital filter comprises a multiplier, one input of which receives the filter coefficients from a memory.

In certain advantageous embodiments proposed, 6 "the output signal of the multiplier is applied to an input of an adder / subtractor whose output signal is applied to a short delay circuit, whose output signal is applied to a long delay circuit Advantageously, the short and long delay circuits respectively comprise 65 short and long span shift registers.

The accompanying drawing illustrates, by way of example, embodiments of the subject of the invention; in this drawing:

fig. la is a block diagram of the basic elements of a voice synthesizer,

fig. lb is a diagram representing the presence of the excitation signals and of Kn coefficient, as a function of time,

fig. 2a and 2b represent a typical grid filter, of the type used in speech synthesizer circuits,

fig. 3 is a diagram representing the arrangement over time of the phases of generation of the intermediate results in a grid filter having N stages,

fig. 4 is a diagram representing the arrangement over time of the phases of generation of the intermediate results in a grid filter having ten stages,

fig. 5 is a general diagram of an embodiment of a digital filter equivalent to a grid filter,

fig. 6 is a table containing the list of the various intermediate results available in the filter of FIG. 5, in different phases of a cycle,

fig. 7 is a general diagram of another embodiment of a digital filter equivalent to a grid filter,

fig. 8 is a table giving the list of the various intermediate results available in the filter of FIG. 7, in different phases of the cycle,

fig. 9 is a diagram of the network multiplier used in the digital filter,

fig. 10a-10d are logic diagrams of the various elements represented in FIG. 9 and fig. 11 shows a generalized form of digital filter. Fig. 1 shows, in the form of a block diagram, the basic elements of a voice synthesizer system. This voice synthesizer circuit includes a multi-stage grid filter 10, which digitally filters an excitation signal 11, using filter coefficients KrKn. The grid filter 10 emits at its output a digital signal 12 which is converted into an analog signal by a “digital / analog” converter 13. The output signal of this converter 13 is transformed into audible sounds by a loudspeaker 14 or by some other means of converting an electrical signal into sounds. It is understood that an amplifier can be used between the converter 13 and the loudspeaker 14, to amplify the analog output signal of the converter 13 to the level required by the loudspeaker 14.

The excitation signal (U) 11 is generally taken from one of two sources, one of which is a “voice” source 15 and the other of which is a source of “different signals of a voice” 16. A digital switch 17 determines which of these two sources is used. The source of the “voice” signals 15 is used when it comes to generating the sounds for which the human vocal cords (or vocal folds) vibrate during speech, such as for example the sound of the first E in “Eve " The rate at which the vocal folds open and close determines the "pitch" of the generated sound. The source "of signal different from a voice" 16 is used when it comes to generating sounds such as F in "file" for which the vocal folds are kept open while air is forced d '' go there to the places of voice training. Thus, the fact that one uses one of the particular sources 15 or 16 depends on the kind of sounds that one wants to generate. Typically, the "different voice signal" source 16 generates a random digital signal while the "voice signal" source 15 generates a periodic digital signal. The digital data delivered by the “voice” source 15 and by the “different from a voice” source 16 can naturally be stored in one or more semiconductor memories of the “read only” “ROM” type. Preferably, however, this data is stored in a code format, for example as a step or in a code operating a random number generator. Thus, these data are usually first decoded before the random or periodic data (for example signal V) is delivered to the filter 10. Naturally, depending on the way in which these data are stored.

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born, it may not be necessary to have the switch 17. filter coefficients, we can refer to the previous article

When the data is stored as a step or as mentioned "Linear Prediction of Speech".

code activating a random number generator, a factor Thus, in this embodiment, the rate of the amplification data A is preferably also stored in the output to the converter 13 will be 10 KHz and the upper limit

ROM memory. The amplification factor A adjusts the lower frequency signal of the synthesized speech which will be obtained with constant amplitude V from the “voice” source 15 or from that of the converter 10 will be 5 kHz. Naturally, the source cadence “of signals different from a voice” 16 for producing the data can be modified, if desired, this being a matter of excitation signal V wanted for the filter 10. choice at the discretion of the manufacturer. For example, a given cadence

The excitation signal 11, which in general takes up or imitates those of 8 KHz will result in a synthesis having a fronfunctions of the vocal electis, is modified by the grid filter 10. Maximum response frequency of 4 KHz.

This counterfeits or generally imitates the function of the golds. We will now consider figs. 2a and 2b which show the vocal ganes which filter the sounds generated in the vocal folds. block diagram of the grid filter 10. In fig. 2a, this filter is

The filter coefficients Kj - Kn reflect the shape (i.e. shown as comprising ten stages, Sj-S ^, each of these

the resonances) of the vocal tracts during the emission of speech. ci being equivalent to the stage represented in fig. 2b. For the

Consequently, the coefficients Kt - Kn are periodically convenience of illustration, only three stages are shown readjusted to follow the shape changes of the channels - in detail in FIG. 2a. The input signal of stage S10 is the shim signal and they can be stored, at the same time as the excitation 11, and the output signal 12 of stage Sj is applied

data from sources of voice signals and different signals to converter 13 (fig. la). It will be understood that the signal of a voice, in a memory of the “read only” type of output 27 of stage S10 is not used and that one could, if

(ROM). 20 we wanted, delete the adder 27a and the multiplier

Fig. lb shows, in graphic form, the. sign to 27b in this floor.

output of the signal source "different from a voice" 16 and of the signal source "voice" 15, as a function of time. Here the ^ 8-2b shows a single stage Sn of the grid filter 10.

“voice” signal source 15 is shown as emitting An input signal from this stage, Yn + 1 (i), is applied as a repeating pulse with a period of 5 ms, which causes 25 1ue of input to a adder 26 whose output signal corresponds to a frequency of 200 Hz. This "step" corresponds to es * (i) - The other input signal from 1 adder 26, which is the sound of voice in the domain of many voices women. applied to this adder as a sub input signal

Since men typically have a pulling voice, is drawn from the output of a multiplier 19 which multiplies a lower "step" frequency, a source of mascu voice- By coefficient Kn the output signal bn (i — 1 ) d a line circuit would emit less frequent pulses. 30 delay 22. The output signal of this delay circuit 22 is

The “voice” source 15 is shown as emitting des also applied to an adder 21 which also receives,

pulses at a period corresponding to the "step" of the voice on its input *, the output signal of a multiplier 20.

of somebody. It is understood, however, that these pulses Çe latter multiplies by the coefficient K „the periodic output signal Yn can be replaced by other functions p - of adder 26. The output signal of 1 adder 21

periodic, like for example that of a sine wave 35 is b_n + 1 (0- As we can see, the indices according to the desi-

damped (decaying sin wave) or the function called data generations Y and b define 1 stage in which this

"Chirp function" which starts with a period related to the data is used, while the number which then appears

"not". The source 16 of “signal different from a voice” is represented in parentheses indicates the rank of the cycle in which these data

felt to be emitting a random signal. born are born. The delay circuit 22 provides a function

The coefficients for the grid filter 10 are shown at the 40 ^ on delay of a cycle time interval, as shown in fig. lb as being re-established every five ms. It is very clear ®tre obtained by a shift register, for example. Once, however, the rate at which the coefficients of the filter during each cycle interval, a new grid data point 10 are re-established is a matter of choice left to cons- (i) or Yn (i) is delivered to 1 stage S10 as a tractor signal. If the coefficients are readjusted more frequently, the excitation 11. Thus, for each stage of the grid filter 10,

grid filter 10 will model the dynamics of the vocal apparatus “two multiplications and two additions must be made in a way that corresponds even better to reality, but during each cYclf> cf which means that, by admitting the cadence, this will be at the cost of a larger amount of data using the data shown in fig. lb, these four operations must gasiner in the aforementioned ROM memory. Naturally, be performed in all stages of the 10 in 100 grid filter

a less frequent readjustment of the coefficients will have the op- microsecond effect. It was relatively arbitrary that posed. However, it was found that by readjusting the coefficients 50 ten stages had been assigned to the grid filter 10 of FIG. 2a,

approximately every five milliseconds or so every 1 skilled person will understand that since the

dence of the same order, we obtained as a result a word of sound that 1 we wish to synthesize using a human grid filter of very high quality synthesized by the grid filter * ® varies according to this choice, it is in fact advantageous to have 10 with reasonable requirements as for the number of data this filter in grid 10 with ten stages since that makes it possible to synthesize

to store. 55 be a Paro'e which can hardly be distinguished from a true human word.

The time axis in fig. lb has been divided into intervals of We see that, during each elementary cycle interval, one hundred microseconds. These intervals correspond to the cadence. The ten stages of the grid filter 10 must perform twenty operations of the data from the “voice” source 15 and from the source of multiplication tions and twenty different addition / subtrac-signal operations d 'a voice' 16, as well as the cadence of 60 tion. We realize on the other hand that these operations do not data received and delivered by the grid filter 10. In addition, can not all be performed simultaneously, in this sense although the source of "different signals of a voice" 16 and that, for example, Y10 must be calculated before Y9, which must be a source of "voices", appears from fig. lb, send calculated before Ys, etc., during each time interval of cycle analog signals, it is quite clear that these signals are in fact given. Furthermore, during the same cycle interval, the don-digital signals whose amplitudes have the values represented 65 ^ -bj must be calculated and stored in the trails and which are readjusted according to the intervals shown along long circuits at delay 22 of each stage, in order to be able to be used from the time axis of FIG. lb. For further information during the next cycle interval. The data Y and b scroll about the obtaining of the amplitudes "or magnetudes" denied in connection with FIG. 2b are also shown for

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stages Sj, S9, and S10, in fig. 2a. The equations expressing the input mations at the instant of the first time interval Tl,

relationships between the different data Y and b are presented and the output information of the filter, Y15 becomes available in the ins-in table I at the end of this detailed description. We have both the time interval TI 1. We can see, by comparing the well understood that the data Y and B, as well as the coefficients. 4 and table I, that the different cient input information Kn, are numbers expressed by several digits, the 5 required for the multiplication operations are available coefficients K] -K10 which can vary between the equivalents when they are necessary and that the various bad information of -I-1 and - 1 and being periodically readjusted by an input for the addition operations are also available which will be described later. when they are needed. We can see more,

Fig. 3 shows, in a representative form, the differences, considering fig. 4, that an addition operation (which takes the intermediate intermediate results obtained from the multipliers and preferably a 10 time interval) is started and completed adders of a grid filter having N stages, the horizontal axis- at each time interval and that a multiplicative operation corresponding to time while the vertical axis represents tion is similarly started (and completed) during each of the different stages of the grid matrix 10 to N stages. In the time interval, despite the fact that the particular operation of the Nth stage for example, we have the intermediate results - Kn multiplication which begins then will be completed only eight inter- • bn and Kn • Y „, which are generated respectively by multiplicates of time later. An apparatus allowing these cateurs 19 and 20 to be produced (fig. 2b) and the intermediate results Yn and operations will now be described in detail in conjunction with the bn + 1, which are obtained respectively from the adders 26 and fig. 5.9 and 10a-10d.

21 (fig. 2b). As far as time relations are concerned, the result- We have already indicated that a multiplication operation and an intermediate state - K „• bn must be generated before Xn addition operation are each brought to begin preferably.

can be obtained. On the other hand, Yn must be generated before 20 rence at each time interval. In fact, the number of inter-that K „• Yn can be generated, and Kn ■ Yn must be generated times in a cycle is preferably double before bn + 1 can be obtained. According to the time scale of the number of stages of the equivalent grid filter. Thus, for indication, the addition operations are carried out, as indicated by eight-stage or twelve-stage grid filters, the filter qué, during a time interval of five microseconds, tanigital equivalent will preferably have sixteen respectively or say that the multiplication operations take time plus twenty-four time intervals per cycle. It appears with evi-long. Regarding the relations of the generation of results considering Figures 3 and 4 as the number of intermediate states in the different stages, we can see that time slots allocated for a multiplication operation information output bn an addition operation must be partly dependent on the number of intervals that one has in an available before the multiplication operation - Kn • bn cycle. Thus, eight time intervals can be used to start, which is shown in the drawing by the arrows 30, the multiplication operations in an equivalent digital filter 25. This requires that a “non-operation” period 23 be at one matrix with ten stages, while six time intervals inserted between the operation of addition bn + 1 and the operation of multi- can be used for the operations of multiplication in plication - K „• bn, if only one operation d addition and a digital filter equivalent to an eight-stage matrix, assuming a multiplication operation is triggered during each as long as the filter scheme (in digital equivalence) of the given time interval figures of five milliseconds, as is 35 3 and 4 be followed. However, it will be obvious to the skilled person visible in FIG. 3. The “non-operation” periods 24 are that the number of intervals for a multiplication operation

also inserted after the other additition operations, tion tends to dictate the number of bits which can be multiplied, before the multiplication operation which follows them, for reasons that is to say tends to limit the number of bits usable for symmetry. Thus, we can see that all the operations indi- represent the coefficients Kn. In most applications, the number of bits allocated for the coefficients Kn can be 40 in all stages of the N-stage grid filter, depending on whether they are accomplished concurrently in the order shown in FIG. information processing diagram of fig. 3 and 4, will be sufficient-3, the appropriate intermediate results becoming available enough to lead to a synthesis of very accepted words - when they are necessary. Fig. 3 the general and applicable nature. If, however, an even greater precision is desired, the reliability of a digital realization of a multi-stage grill filter, for the representation of the coefficients Kn, it is possible to provide for a fact to which we will come back again later. We understand 4s not to have at each time interval of the cycle an operation although the representation of FIG. 3 shows the operations which multiply and an addition operation which begin, some are carried out during only one of the aforementioned time cycles, certain phases of delays having then to be inserted in different time intervals of 5 ms for an operation of 'addition, moments during the cycle. Naturally, the cycle will then take place, although being a matter of choice left to the manufacturer, has been a longer time to complete, which will decrease the rate chosen to this value given its compatibility with the data function (and therefore the frequency response) of the system, operation of the P-channel MOS integrated circuits. Naturally, as can be seen in FIG. 4, the intermediate results another additional time interval could be used. K10 ■ Y10 and bn are obtained or can be obtained, despite Iis, if desired. that, as has been mentioned in connection with FIG. 2a, these

Fig. 4 is a representation similar to that of FIG. 3. particular intermediate results are not required for a However, the representation of fig. 4 concerns the realization 55 digital realization of the grid filter. However, we note in digital the equivalent of a grid filter 10 with ten stages, and by connection with fig. 5 that it is most often easier to leave elsewhere, the horizontal axis has been extended to allow the repetition (and to ignore) these intermediate results K10 • Y10 and feeling of more than one cycle. We see on the other hand that the cycle has Bn (or some other numbers) rather than introducing a summer divided into twenty time intervals T1-T20, each of them inhibition in the apparatus to prevent it from performing these cal-preferably having a duration of the order of five microseconds, & o asses. We will now describe how the mul-well operations, as, as already mentioned, other multiplication durations carried out by the multiplier 18 (fig. 1) can also be chosen. In fig. 4, we have also indicated accomplished also in place of the calculation K10 • Y10 in the apparatus, the cycles, by their rank, that is to say (i— 1), (i) and (i + 1), this Fig. 5 represents the block diagram of a digital realization to facilitate the comparison of the availabilities of the results of an equivalent of the grid filter 10. This filter comprises a intermediate in the filter 10 with the requirements arising from the network multiplier 65 30, an adder / subtractor circuit representing the filter 10 in mathematical formulas in the 33, a delay circuit for a period 34, a table shift register I. 35 and a latch memory 36. The data supplied to the input

The excitation data U are applied as information and taken from the output of these different units each of the

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twenty time intervals T1-T20 (for the equivalent of a ten-stage grid filter) are given in the lists in fig. 6. Referring now to Figs. 5 and 6, it can be seen that the network multiplier 30 performs the multiplications which are made by the multipliers 19 and 20 of each stage of the equivalent grid filter according to FIGS. 2a and 2b. The network multiplier receives, by lines 32, the coefficients K ^ —K10 which are stored in a memory in stacks K 31, and, via the omnibus line 40, either a data item Yn or a data item bn. The stack memory K 31 preferably comprises ten shift registers, each of them having ten stages. The information stored in the stacking memory K 31, indicated in table II at the end of this detailed description, is transmitted to the network multiplier 30 by the lines 32. This network multiplier 30 starts a new multiplication operation at each time interval, as shown in fig. 4, i.e. approximately every five microseconds. The network multiplier 30 comprises, as will be further explained in FIG. 9, preferably eight stages, a series of shift addition operations being performed while the data propagates through these eight stages, in a manner which achieves their multiplication by the appropriate coefficient Kn, received from the memory at stacks 31 which stores these coefficients. A multiplication operation lasts forty microseconds. However, since a new multiplication operation begins every five microseconds, eight multiplications are always in progress at different stages of progress, at any given time. The computation period of the network multiplier 30, comprising eight time intervals, can be found in FIG. 8 considering the places where the input data appear and the places where the output result appears. For example, the inputs of the multiplier at the interval T1 are found at the output of the multiplier, in the form of product, eight time intervals later, that is to say at the interval T9. The coefficients stored in the stack memory K 31 are stored as nine-bit numbers plus one additional bit for the information of the sign. As mentioned, these nine bits form numbers in the range of - 1 to +1 (decimal equivalents), which, as we will see, simplifies the structure of the network multiplier 30.

The output signal of the network multiplier 30 is applied to the adder-subtractor circuit 33. This output, in the preferred embodiment, is a channel with thirteen parallel bits: twelve data bits and one bit for sign information . Those skilled in the art will understand, however, that the number of bits in a data channel is a matter of choice left to the constructor. The other input of the adder / subtractor circuit receives: the excitation signal 11 at the time interval T1, the output of the adder / subtractor circuit 33 itself during the time intervals T2 — T10, the signal output of the shift register 35 during the time intervals T11-T19, and the output signal of the lock 36 at the time interval T20. This second input of the adder / subtractor circuit 33 is shown, for the convenience of the illustration, as being controlled by different unipolar switches with a single armature 37a-37d; however, it is understood that switches with solid electronic components will preferably be used to perform these switching functions, as well as for the other switching functions described. The output signal from the adder / subtractor circuit 33 is applied to the switch 37b, to the switch 38a and as an input signal to the interval delay circuit 34. The output signal from the adder / subtractor circuit 33 is also provided in a thirteen-bit parallel channel and it is delayed by a time interval in circuit 34 before being applied as an input signal to shift register 35 and switch 38b. The shift register 35 stores the information of the thirteen-bit channel in thirteen elementary shift registers, each of which has eight stages. The shift register 35 is arranged to perform shift operations only during the time intervals T12-T2. The output si-5 of this shift register 35 is applied to switches 37c and 39. Switch 39 is closed (on) at the time of time interval T20 to introduce the output signal Yx of the filter into the lock memory 36. The output 12 of this lock memory 36 is connected to the digital / analog converter 13 (fig. la) as well as to the switches 37b and 38c.

Switch 37b is closed (on) during time intervals T2-T10, switch 37c is closed (on) during time intervals T11-T19, and switch 37d is closed (on) at time interval T20. The switch 38a is closed (passing) during the time intervals T13-T1, the switch 38b is closed (passing) between the time intervals T3-T12, and the switch 38c is closed during the time interval T2. The other electrodes of the switches 38a, 38b and 38c are connected to the input of the networked multiplier 30, via the bus line 40.

In fig. 6 is reported the list of the various intermediate results which intervene in the circuit of FIG. 5 during the time intervals T1-T20. By briefly considering this 25 fig. 6, it can be seen that one of the inputs of the multiplier receives the coefficient information Kn while the other input receives different information depending on which of the switches 38a, 38b, 38c which is closed (on). During the time interval T1, the switch 38a is closed (on), as already mentioned, so that the output signal of the adder / subtractor 33 in this case b2 (i— 1) , is applied as an input signal to the multiplier. At the same time, the other input of the adder receives the excitation signal U (i). During the time interval T2, the other input of the multiplier 35 receives the information bt (i— 1), which, as shown in FIG. 5, was taken from the output of the latch 36 via the switch 38c. The output information of the lock 36 is then, according to FIG. 6, Y1 (i— 1), but, by calling on the last line of table I, we remember that the information bx (i) is established as identical to the information Yx (i) delayed , i.e. information Y! (i— 1). During this same time interval T2, the other input of the adder receives the information which is delivered by the output of this same adder, that is to say, in this case, Y10 (i). During the 45 time interval T3, the input signals of the multiplier are K10 and Y10 (i) coming from the output of the time delay delay circuit 34. Naturally, the result of this multiplication will not be available before the time interval Tll, and at that time it will be delivered as an input signal to the circuit 50 adder / subtractor 33. During this time interval Tll, the other input of the circuit adder / subtractor 33 will receive the information leaving the shift register 35. The first term loaded in a significant way on the shift register 35 is the information b10 (i - 1), which appears at the output of this register 55 offset 35 during the time interval T2 and which remains available at this location since the shift register 35, as previously mentioned, makes no offset between the time intervals T3 and T1.

During the time interval T13, the input information of the network multiplier 60 is again supplied by the output of the adder / subtractor circuit 33, via the switch 38a. At the time interval T20, the term Yx (i) is delivered to the lock memory 36 from the shift register 35, and the information which until then was at the output of this lock 36, c that is to say Y1 (i— 1) is applied to the other input of the adder / subtractor circuit 33 via the switch 37d, to constitute there, as already mentioned, the term bi (i— 1). So the memory lock 36

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stores the output information from the Yt filter which will remain there for the duration of the next cycle.

We have just provided explanations concerning the block diagram of FIG. 5. It should be noted that the design of fig. 5 can also be applied to a decimal filter equivalent to an N-stage grid filter having an M-stage multiplier (for example, it can have M plus two bits in the coefficients Kn), provided that a shift register introducing a delay equivalent to N— M - 2 time intervals is inserted between the adder / subtractor circuit 33 and the delay circuit at a time interval 34. The connection with the switch 38a is then made from the output of this register at additional shift and the delay caused by the shift register 35 should then be equal to N + M— 1. This generalized form of the digital filter is shown in fig. 11. In the embodiment of FIG. 5, N— M— 2 is zero, so that no further delay is required in this embodiment. In the embodiments described in conjunction with FIGS. 5 and 6, N + M— 1 is equal to seventeen, which reflects the number of time periods between the moment when the data are applied to the shift register 35 and the moment when these data emerge from this shift register . For example, in fig. 6, the data b2 (i-1) is inserted into the shift register 35 at the time period T2 and it emerges from this register at the time period T19, that is to say seventeen periods later . Note that in this embodiment, the shift register 35 comprises only eight stages, but the additional delay occurring during the time periods T3-T11 corresponds to the time during which the shift register 35 does not shift . These nine time periods correspond to the time when the data Y2-Y10 is available at the output of the timed circuit 34, the delay of which corresponds to one period. This data does not need to be entered into the shift register 35, as can be seen in FIG. 6. Thus, the number of stages of the shift register 35 plus the number of periods per cycle where the data (if any) are not shifted in the shift register 35 is equal to the delay equal to N + M— 1 periods time by shift register 35.

As can be seen, the circuit illustrated in figs. 5 and 6, equivalent to a ten-stage grid filter, performs the filtering operations required by the grid filter 10 of FIG. there at a reasonable data rate. For example, in the preferred embodiment, the excitation data 11 is applied at a frequency of 1 Hz (that is to say every hundred microseconds), and the basic addition operations in the adder circuit / subtractor 33, as well as the multiplication operations in the network multiplier 30 and that the shift operations in the delay circuit in the time interval 34 and in the shift register 35 are carried out during the time interval nominal five microseconds. As is well known to those skilled in the art, such speeds are well within the possibilities of a device with P-channel MOS elements in large-scale integration, so that the filter of FIG. 5 can be incorporated into a relatively inexpensive P-channel LSI MOS wafer (type) for generating synthesized speech or complex waveforms.

It is obvious that the basic arrangement of the filter in fig. 5, equivalent to a ten-stage grill filter, is also applicable to digital filters equivalent to grid filters having another number of stages. The number of ten stages was selected as the preferred embodiment for the filter, since a ten-stage grid filter for the linear predictive speech synthesis circuits was selected as the standard of use by the Department of Defense of the Government of the United States of America. It should simply be noted for those who, considering the practice of this invention, would like to use a digital filter

equivalent to a grid filter with a different number of stages, that the number of intervals into which a cycle is divided must be at least twice the number of equivalent stages. Thus, in the preferred embodiment, the number of time intervals (twenty) is twice the number of equivalent stages (ten). So if, for example, a digital filter equivalent to a twelve-stage grid filter was desired, the number of time intervals per cycle should be at least twenty-four and the basic design just described io is expected to expand significantly. It should be noted that for a digital filter equivalent to a twelve-stage grid filter, the grating multiplier 30 should use ten time intervals to complete a multiplication if the basic scheme previously described is followed, i.e. if an addition operation and a multiplication operation were to start during each time interval. This can be seen from fig. 3, establishing N equal to twelve and completing the diagram of this figure 3 in a corresponding manner. Naturally, if a duration of five microseconds was main-2o naked for each time interval, the data rate, having to accommodate the version with twelve stages, would be lower than that which one has in the version of the filter with twelve floors. It should also be noted that, by increasing the delay time in the network multiplier 30, the number of bits of the coefficients K ^ -K ^ could be increased, increasing the total from ten bits to a total of twelve bits.

Similarly, if a digital filter equivalent to an eight-stage grid filter was desired, the number of cycle time intervals should be at least sixteen, and giving N the n / a value eight in fig. 3, it can be seen that the propagation time through the multiplier 30 would then be six time intervals. In this case, the use of the network multiplier, which will be described in detail below, would limit to eight the number of bits in the coefficients taken from the stacking memory K 35 31. However, as already mentioned in connection with fig. 4, it is possible, in certain embodiments, to use even more time intervals to carry out a multiplication operation. This might be desirable - this being a matter of choice - if greater precision of the 40 Kn coefficients was required. Higher precision would require more bits for the Kn coefficients, which in turn would imply admitting greater delay through the grating multiplier 30. The basic design of the equivalent filter in FIG. 5 would be somewhat modified by the fact that then a multiplication operation and an addition operation would not have to start at each time interval. It is obvious that in such a case some of the intermediate results obtained inside the filter should be temporarily stored, which would require the intrusion of additional memory elements into the filter of FIG. 5. We will not discuss here the detail of the modifications of this kind which would be possible, such modifications of the digital realization of a grid filter would be in the field of what the specialists of the digital circuits can know. 55 We have previously mentioned that the intermediate results K10 • Y10 (i) and bn (i) were generated by the digital filter of fig. 5, but that these intermediate results were not used in the sense that they are not required to produce the grid filter 10 of FIG. the. Now, remembering that the data given V coming from the source of “voice signal” or “of signal different from a voice” is multiplied by an amplification factor A, by means of a multiplier 18, in the circuit of classical speech synthesis of fig. la, we see that this multiplication can be done using the network multiplier 65 30 during the time when the intermediate result K10 ■ Yio (i)

would otherwise be generated by the network multiplier. An embodiment of a digital filter realizing this multiplication V (i). A is shown in fig. 7. Furthermore, FIG. 8 provides a

633,922

8

list of the various intermediate results generated in the circuit of fig. 7.

We will now briefly consider figs. 7 and 8 where it will be seen that this circuit (including the intermediate results which are generated there) is similar to the circuit of fig. 5, with the exception of the following modifications: The reference signs of FIG. 7, which are generally the same as those of FIG. 5, are decked out with a premium allowing easy identification. The data V, to be multiplied by the multiplication factor A, is applied to an input of the network multiplier 30 'via a switch 38d', during the time interval T3, instead of l application at this time of the output signal of the delay circuit of a period 34. At the time interval T11, when the multiplication has been completed to form U (i + 1), that is to say say A • V (i + 1), zero logic levels are applied to the other input of the adder / subtractor circuit 33 ', in place of the information b10 (i— 1) coming from register 35. Naturally , the two pieces of information, of coefficient Kn and of amplification A must be introduced into the stacking memory K 31 '. As can be seen in fig. 7 and 8, this embodiment incorporates the function performed by the multiplier 18 in the case of FIG. la in the digital embodiment of the grid filter 10. The data stored in the stacking memory K 31 ′ are indicated in table III at the end of this detailed description. The amplification factor A is preferably readjusted at the same rate as the coefficients Kn are readjusted in the stack memory K 31 '.

We will now consider fig. 9 which represents, in the form of a block diagram, the network multiplier 30. The lines 32—1 to 32—9 respectively receive from the least significant to the most significant the bits of the coefficient data coming from the stack memory 31 by the intermediate of lines 32. Line 32-10 receives from the stack memory K 31 the data relating to the sign. Another input information for the network multiplier 30 is received via the bus line 40. The lines 40-1 to 40-12 of the bus line 40 carry the bits respectively from the least significant to the most significant and line 40-13 carries the sign information of the feed 40. In FIG. 9, we can see a whole network of elements having the reference signs A, B, C or D (the elements without reference signs are elements of type A, that is to say correspond to FIG. 10a. These elements AD correspond to the circuits represented in FIGS 10a-10d, respectively, reference will be made briefly to these figures 10a-10d. The circuits in question are each represented surrounded by a frame line in dotted lines. beyond this framework line and their relative position corresponds to the way in which they are put in relation by conductors which connect them, in Fig. 9. On the latter, the elements are arranged on eight horizontal lines and twelve columns. eight lines correspond to the eight stages mentioned above of the network multiplier 30. These stages are identified on the right side of Fig. 9 and they include the eight shift register cells 31 coupled to line 40-13. to the thirteen bits of digital data (on lines 40-1 to 40—12) entered as inputs on the network multiplier 30. The data on lines 40-1 to 40-13 propagates through the network multiplier 30 stages by stage in the manner of what happens in a shift register, at the same time that they are multiplied adequately in the multiplier 30. Thus, the time of propagation through any given stage is of the order of the interval of aforementioned time of five microseconds.

Line 32-1 of the stacking memory K 31 is coupled to an input of twelve AND gates 52—1 to 52—12, the second inputs of which are respectively coupled to one of lines 40-1 to 40-12. ET gate output signals

52-12 to 52—1 are applied to the partial sum inputs of type A and B elements of stage 1 (see fig. 10a and 10b).

Lines 32—2 to 32-8 are coupled to the K-stack inputs of type A elements (fig.

510a) in stages 1 to 7 of the network multiplier 30 respectively. Line 32-9 is coupled to the "line 32-9" input of type C elements of stage 8 (see fig. 10c). The data on lines 40-1 to 40-12 are brought to the “data-in” inputs of the elements of stage 1 and, by this one to the elements of stages io 2 to 8 via the outputs “data -out 'of these different elements. The partial sum input of the elements of stage 1 receives the output information from AND gates 52-1 to 52-12, and, in the following stages, this input receives the partial sum output of the next most significant bit (from the previous stage), 15 with the exception of the partial sum entry of the elements in which the most significant bits are already found, case in which the partial sum entry "partial sum" receives its signal from the carry-out output of the most significant bit of the previous stage. Otherwise, the carry-over connections of all the elements are connected to the carry-in inputs in each stage.

In the circuit of fig. 10a, the data coming from the stacking memory K (K-stactlc) 31 determines the connection of the output “partial sum out” either directly, in transit 25 through gate 60, with the input “partial sum in” either , via gate 61, with the output of the EXCLUSIVE OR gate 62. An AND gate 63 and an EXCLUSIVE OR gate 64 operate in response to the two data “data-in” and “partial sum in”. The EXCLUSIVE OR gate 62 responds to the output of the EXCLUSIVE OR gate 64 and to the “carry in” input. An AND gate 65 operates in response to the output of the EXCLUSIVE OR gate 64 and to the “carry in” input and the output of this gate is brought, parallel to the output of the AND gate 63, to the input of an OR 66 gate which delivers the "carry out" output signal. The output 35 "data out" corresponds to the input "data in", delayed by a shift register section 67 comprising for example two inverters. As can be seen in fig. 10c, an element of type C is identical to an element of type A except for the fact that it does not include an output connection "data out" and that it is therefore not provided with sections of shift registers 67.

Fig. 10b shows a type B element which simply provides, on the one hand, a “data out” output coupled via shift register elements 67 ′ with the “data in” input, and on the other hand , a “carry out” output coming from the output 45 of an AND gate 68, the two inputs of which respectively receive the “data in” and “partial sum in” input information. In fig. lOd, we see that a type D element simply provides a "carry out" output which comes from an AND INVERSE 68 'gate whose inputs receive the signals "data in" and "partial 50 sum in".

As can be seen, a new partial sum is calculated for each stage, this calculation including the necessary transfer of the carry-over information between the elements of a stage, but the partial sum output “partial sum out” remains unchanged if 55 the line information coming from the stacking memory - K is a logic level zero or is added to the data “data in” to provide the output value “partial sum out” if the information on the line coming from the memory for memorizing the coefficients 31 is a logic level "1". The 60 partial sums are shifted to the least significant bit locations when the data is shifted through the grating multiplier. Naturally, the digit of the least significant position is lost on each stage of the network multiplier, but, since the indication of coefficient Kn pro-65 coming from the stack memory 31 of the coefficients K corresponds to a number located in the decimal range from - 1 to + 1, this is implied by the fact that the relative precision remains the same. Thus, if zero ligic levels appear on the

9

633,922

lines 32-1 to 32-9, the output of the network multiplier 30 will be discussed in detail, since these are classic elements although a logic level zero and, conversely, if the data on the known in themselves . The adder / subtractor circuit 33

lines 32-1 to 32-9 are all logical levels 1, the information (or 33 ') receives information provided with signs on its two mation entering on the omnibus entry 40 will be transmitted in entry way and it must determine if it must perform an unchanged operation at the output of the network multiplier 30. For the 5 subtraction or addition, taking into account the particular sign other possible combinations of data on lines 32—1 to be introduced with each of the two information.

32-9, the data arriving on the omnibus 40 feed will be reduced to an intermediate value between their input value and Table I value zero, this in 29 not possible, depending on the value of the data combined on lines 32 -1 to 32-9. 10 STOREY EQUATION

Because the data shifts through the network multiplier 30 stages by stage, in the manner of what happens Y 10 (i) = Yii (i) K10b10 (i-1) 10 in a shift register, the data from the stacking memory K 31 for the coefficients are distributed “obliquely” Y9 (i) = Y 10 (i) - K9b9 (i-1) 9 as shown for example in tables II and III, to ensure 15 b 10 (i) = b9 (iI) + K9Y9 (i) 9 that the appropriate bit of the appropriate coefficient arrives at the appropriate time on the network multiplier 30. In fig. 10a to Y8 (i) = Y9 (i) - K8b8 (i-1) 8

10c, the timing pulses to operate the b9 (i) - b8 (i-l) + K8Yg (i) 8

circuits like a shift register, as mentioned above

above, are not shown, since it is 20Y7 (i) = Y8 (i) -K7b7 (i-l) 7 circuits well known to those skilled in the art. Such functions of b8 (i) = b7 (i-l) + K7Y7 (i) 7 timing can be established by adding gates controlled by clock pulses to the circuit according to fig. Y6 (i) = 'Y7 (i) - KLgb6 (i-l) 6 10a to 10c, or using a logic of the preparation type and in b7 (i) = b6 (i-l) + K6Y6 (i) 6 loosely conditioned. There is therefore no need to enter here in 25

detail in considerations regarding this timing. Y5 (i) = Y6 (i) - K5b5 (i-1) 5 Returning briefly to fig. 9, we notice b6 (i) = b5 (il) + K5Y5 (i) 5 although the sign information, on line 40-13 is simply transferred, with delay, through the eight stages of multi- Y4 ( i) = Y5 (i) - K4b4 (i-1) 4 network plicator 30, by elements of shift registers 30 b5 (i) = b4 (il) + K4Y4 (i) 4 51, then compared with the sign of the coefficient data coming from memory 31, on line 32-10, by means of a Y3 (i) = Y4 (i) - K3b3 (i-1) 3 gate OR EXCLUSIVE 53, whereby the correct sign is assigned b4 (i) = b3 (il) + K3Y3 (i) 3 to the information that appears at the output of the multiplier, in accordance with normal rules of multiplication. 35 Y2 (i) = Y3 (i) -K2b2 (i-l) 2 By briefly considering figs again. 5 and 7, we denote b3 (i) = b2 (i-l) + K2Y2 (i) 2 which we mainly discussed in detail the network multiplier 30 (or 30 '). The other elements, such as for example the Yx (i) = Y2 (i) - Kjb ^ i-l) 1

adder / subtractor circuit 33 (or 33 ') or the circuit at re- b2 (i) = b1 (i-l) + K1Y1 (i) 1

late in a period 34 (or 34 '), or the shift register 40

35 (or 35 ') and the lock memory 36 (or 36') were not b1 (i) = Y1 (i)

45

Table II

DATA DELIVERED BY MEMORY 31 OF THE COEFFICIENTS + BY TIME-OUT INTERVALS MEM.

Bit line

Tl

T2

T3

T4

T5

T6

T7

T8

T9

T10

Tll

T12

T13

T14

T15

T16

T17

T18

T19

T20

LSB

32-1

k2

K!

K10

k9

k8

k7

KO

K5

k4

k3

32-2

k2

K10

k9

k8

k7

k6

k5

k4

k3

32-3

k3

k2

Ki

K10

k9

k8

k7

Ke k5

k4

32-4

k4

k3

k2

Kx

K10

k9

k8

k7

k6

k5

32-5

k5

k4

k3

k2

Kt

K10

Kg k8

k7

Ke

32-6

k6

k5

k4

k3

k2

Kx

K10

k9

k8

k7

32-7

k7

k6

k5

k4

k3

k2

K!

K10

k9

k8

32-8

k8

k7

k6

k5

k4

k3

k2

Ki

K10

k9

MSB

32-9

k9

k8

k7

K6

k5

k4

k3

k2

K!

K10

SIGN.

BIT

32-10

k9

k8

k7

k6

k5

k4

k3

k2

K,

K10

o

Table III

DATA DELIVERED BY THE MEMORY 31 'OF THE COEFFICIENTS, BY TIME-OUT INTERVALS MEM.

Bit

Line

Tl

T2

T3

T4

T5

T6

T7

T8

T9

T10

Tll

T12

T13

T14

T15

T16

T17

T18

T19

T20

LSB

32-1

k2

K J

AT

k9

Kg k7

KO

k5

k4

k3

k2

Ki

Kio k9

Kg k7

k6

Ks k4

k3

32-2

k2

Ki

AT

k9

K8

k7

k6

Ks k4

k3

k2

Ki kio k9

Kg k7

k6

k5

k4

k3

32-3

k3

k2

K J

AT

k9

Kg k7

k6

k5

k4

k3

k2

K,

kio k9

Kg k7

k6

k5

k4

32-4

k4

k3

k2

Ki

AT

k9

Kg k7

k6

k5

k4

k3

k2

Ki

Kio k9

Kg k7

k6

Ks

32-5

k5

K,

k3

k2

Ki

AT

k,

Kg k7

kfi k5

k4

k3

k2

ki kio k9

Kg k7

k5

32-6

k6

k5

k4

k3

k2

"• i

AT

k9

Kg k7

k6

k5

k4

k3

k2

ki

Kio k9

Kg k7

32-7

k7

Ke k5

k4

k3

k2

k!

AT

k9

Kg k7

k6

k5

k4

k3

k2

ki kio k9

Kg

32-8

Kg k7

k6

k5

k4

k3

k2

Ki

AT

k9

Kg k7

k6

Ks k4

k3

k2

ki kio k9

MSB

32-9

k9

Kg k7

K6

k5

k4

k3

k2

Ki

AT

k9

Kg k7

k5

k5

k4

k3

k2

ki kio

SIGN

32-10

k9

Kg k7

k6

k5

k4

k3

k2

k!

AT

k9

Kg k7

k6

k5

k4

k3

k2

Ki kio

B

Claims (10)

633,922 2 1. Digital filter operating in response to a digital excitation signal and to a plurality of digital values representing filter coefficients, comprising: - a first memory (31; 31 ') for storing a plurality of said digital values, - a multiplier circuit (30; 30 '), - first means (32; 32 ') for coupling said first memory and said multiplier circuit, - an arithmetic circuit (33; 33 ') having an input coupled to said multiplier circuit, - a second memory (34,35,36; 34 ', 35', 36 ') for storing the information leaving the said arithmetic circuit, and - second means (40; 40 ') for coupling the output information of said arithmetic circuit to an input of said multiplier circuit, characterized in that said second means also couple (38C; 38C '), selectively, the output information from said second memory to an input of said multiplier circuit. 2. Digital filter according to claim 1, characterized in that said second memory comprises first and second delay circuits (34,35; 34 ', 35'), the delay associated with said second delay circuit being longer that the delay associated with said first delay circuit, and said second means selectively coupling (38B, 38C; 38B ', 38C') the outputs of said first and second delay circuits to said multiplier circuit. 3. Digital filter according to claim 1 or 2, characterized in that it further comprises third means (37D, 37C, 37B; 37D ', 37C', 37B ') for selectively coupling the outputs of said second memory and from said arithmetic circuit to another input of this arithmetic circuit. 4. Digital filter according to claim 2, characterized in that said second memory further comprises lock storage means (36; 36 ') for temporarily storing the information leaving said second delay circuit, said second means being arranged to selectively couple (38C; 38C) the output of said latch storage means to said multiplier circuit. 5. Digital filter according to claim 4, characterized in that it further comprises third means (37D, 37C, 37B; 37D ', 37C', 37B ') for selectively coupling the outputs of said lock storage means, from said second delay circuit, and from said arithmetic circuit, to another input of this arithmetic circuit. 6. Digital filter according to claim 5, characterized in that said second means comprise first switching means (38C, 38B, 38A; 38C ', 38B', 38A ') for selectively coupling the outputs of said lock storage means , of the said first delay circuit and of the said arithmetic circuit, at an input of the said multiplier circuit, the said third means comprising second switching means (37D, 37C, 37B; 37D ', 37C', 37B ') for selectively coupling the outputs of said locking storage means, of said second delay circuit and of said arithmetic circuit, at said other input of this arithmetic circuit. 7. Digital filter according to one of claims 1 to 6, characterized in that said excitation signal (11) is coupled to said multiplier circuit by said second means (40; 40 '), an amplification factor associated with said excitation signal being stored in said first memory with said digital values. 8. Digital filter according to one of claims 1 to 7, characterized in that said excitation signal is coupled to said arithmetic circuit. 9. Digital filter according to one of claims 1 to 8, characterized in that it is arranged so that each of said digital values is readjusted once during a plurality of cycles, while said excitation signal is readjusted once during each cycle, each of these cycles including a plurality of time intervals during each of which the said multiplier circuit causes a new multiplication operation to begin, the latter taking a plurality of said time intervals to complete. 10. Use of the digital filter according to claim 1, in a voice synthesis device, to produce synthesized human words, in response to said excitation signal and said digital values, the voice synthesis device comprising means (13,14) coupled to receive selected output signals from said second memory and converts them into audible synthesized human speech.