SU886251A1 - Frequency synthesizer - Google Patents

Description

I

The invention relates to radio engineering and can be used in the transceiver equipment of communication systems, in generator equipment.

A frequency synthesizer is known to contain (it is a serially connected reference oscillator, a first pulse shaper, a phase detector based on a 3 K trigger, a low-pass filter, a controlled oscillator, a second pulse shaper, a coincidence element, a first control trigger, a second control trigger, memory trigger, as well as a frequency divider with a variable division factor, the output of which is connected to another input of the phase detector and to one of the control inputs a discriminator of the frequency error sign, another whose control input is connected to the output of the first pulse generator l..

However, the well-known frequency synthesizer has low operation stability.

The purpose of the invention is to increase the stability of the work by expanding the capture band.

To achieve this goal, in a frequency synthesizer containing a series-connected oporsh generator, a first pulse shaper, a phase detector made on the basis of a K-trigger, a low-pass filter, a controlled oscillator,

10 a second pulse shaper, a matching element, a first control trigger, a second control trigger, a memory trigger, and a frequency divider with a variable division factor 15, the output of which is connected to another input of the phase detector and from one of the controls of the inputs of the frequency difference separator The other control, the other input of which is connected to the output of the first pulse shaper, the input of the first pulse shaper, is connected to the setting input of the memory trigger, the output of which is connected to the setting input With the phase detector and frequency error sign discriminator, the first output of the phase detector is connected to one of the memory trigger control inputs, the second output of the phase detector is connected to the other control trigger memory inputs and the frequency error detector, the first output of which is connected to the reset circuit the first and second controllers. Another output of the frequency error sign 1 is connected to the input of the match element, the output of which is connected to the input of a frequency divider with a variable division factor, the output of which is connected to the counting input of the memory trigger and to the control input of the first control trigger, the counting input of which is connected to the 1st input The second pulse generator, the output of the first control trigger is connected to the input of the second control trigger, the direct and inverse outputs of which coejD HewH, respectively, with the third controlling input m discriminator of the frequency error sign and with the installation input of a frequency divider with a variable division factor,. -

A diagram shows the structural electrical scheme of the proposed synthesizer.

The frequency synthesizer contains a controlled oscillator 1, a reference oscillator 2, the first and second shapers of 3 and 4 pulses, respectively, a frequency divider 5 with a variable factor of dividing, which consists of three counters 6.7 and 8 mLups, three switches 9.10 and M factor frequency division and cxefft 12 coincidence, phase detector 13, first and second control triggers 14 and 15, respectively, memory trigger 16, frequency error sign discriminator 17, low-pass filter 18 and coincidence element 19.

The frequency synthesizer works as follows.

Let the frequency of the controlled oscillator 1 be divided by a divider 5 frequency with a variable coefficient

less frequency reference

division,

generator 2. At the same time, the initial detuning is greater than the capture band, but less than the holding band.

In this case, a pulse with a frequency of the reference oscillator 2 preceding the pulse from the output of the circuit 12 coincidence (at the output of a divider 5 frequency with a variable division factor, the pulse frequency, where

N-kosf4n (division divi- sion), sets logic output 1 at the output d of the phase detector 13, at the output of cxebfti 12, a logical one is also set for the output of the other. This signal does not affect the discriminator 17 of the sign of the frequency error performed on the 3-K-trigger. On the other hand, impulses with a reference frequency from the output of the first driver of the 3 pulses overturn the J-JK trigger of the frequency error sign discriminator. The output signal from the coincidence circuit 12 also goes to the counting input of the memory trigger 16, to the setup (R input) input of which it comes from the output of the first driver 3 pulses and flips the memory trigger. in position G on the 5th exit.

Simultaneously, from the output of the second control trigger 15, the pulses of the input to the control are the input of the discriminator of the 17th sign of the frequency error and according to) its color) from its initial position

The control voltage at the output of an IS low-pass filter increases, and with Frequency the frequency of the controlled Torus: 1 increases rapidly. Due to the effect of the first 14 and second 13 control triggers, the pulse of the second control trigger affects the discriminator 17 of the sign of the frequency error and the counters 6.7 and 8 pulses, the divider 5 of the frequency with a variable division factor is forcibly reset. with the frequency f .. In this case, the final state 1 of the frequency divider 5 is proportional to the frequency f, and the phase detector 13 is in this position,. that the control voltage is as large as possible.

Claims (1)

1. USSR author's certificate No. 479215, cl. H 03 V 21/02, 1973 5 {prototype,