SU869061A1 - Circular counter - Google Patents

Description

(5-1) 1 OLD COUNTER

I

The invention relates to a1 tomato and computer technology and can be used in the implementation of technical means B of these areas.

A ring counter is known, which contains an input bus, a VI-bit shift register Tia for LC, flip-flops, an AND-NE element, and an AND E element.

A disadvantage of the known device is the large time of exit from the forbidden states into which the device can get as a result of the interference.

The closest technical solution to the present invention is a ring counter containing an input bus, a U1-bit shift register for D triggers, and an element whose inputs are connected to inverse outputs of all bits of the shift register except the last .35 the shift register bit is connected to the output of the AND element, the input bus is connected to the clock inputs of all the shift register bits. With

when applying clock pulses to the input ujviuy of a known device, a single unit is moved in the bit field of the counter. In case of extra units, the element VI holds the first bit of the shift register in the state O until the spurious state is corrected.

A disadvantage of the known counter is the large exit time from the requested-to-states, since in the worst case this time is f | periods of clock frequency.

The purpose of the invention is to reduce the time to exit from forbidden states.

Claims (2)

The delivered ael is achieved by those. that in the ring counter containing the input bus, the I-bit shift register on the D-trigger element I, whose inputs are connected to the inverse outputs of all the bits of the shift register except the last, the p-input of the first bit of the shift register is connected to the output of Z input shiva is connected to the clock inputs of all bits of the shift register, in each bit of the shift register, the second and last, the element OR is entered, the output of which is connected to the input of the setting at zero of this bit of the shift register the shift country, except the first one, the inputs of the OR element are connected to the direct outputs of all subsequent bits, the shift register, in the first bit of which the inputs of the OR element are connected to the direct outputs of all subsequent bits of the shift register, except the last, the inputs The last and last bits of the shift register are connected respectively with the direct outputs of the last and first bits of the shift register. The drawing shows as an example the diagram of a six-bit ring counter. - drawing; output bus 1, bits 2-1-2-6 of the shift register (respectively, starting from the first stage) nai B-triggers, element OR 3-1-3 4, respectively, of the bits of the shift register, element AND 5. In the drawing The input bus 1 is connected to the clock inputs of the shift register bits — the bit register bit is connected to the output of element 5, whose inputs are connected to the inverse outputs of the bits of the shift register — the inputs of the setting to the zero of the bits of the shift register are connected respectively to the outputs of the elements OR, direct output bit 2-6 register with engine and direct output of the shift register; the inputs of the OR element are connected to the direct outputs of the bits — 2–5 shift registers; the inputs of the element OR 3 are connected to the direct outputs of the bits - shift register ;. The inputs of the OR OR 3 are connected to the direct outputs of the discharge register of the shift and the inputs of the OR element are connected to the direct outputs of the bits of the shift register. The device works as follows. When applying clock pulses on the bus 1 in the ring counter circulates one unit. When the state of the counter O0., .01 is at the output of the element And 5, there is a single potential, therefore, when the next clock pulse arrives, the counter goes into 10 ... 00 ei4 The unit potential at any output of the shift register confirms the state of a logical zero in one for several other bits of the shift register, affecting their zero setting inputs via OR or non-occurring elements. When forbidden states appear at the outputs of the OR elements and at the outputs of the bits, signals of the logic unit appear that set the counter to the allowed states, the maximum correction time being determined by the sum of the delay of the trigger setting and the delay of the OR element. Thus, the time of exit from the forbidden states in the proposed device is one times less than in the known device. The invention of the ring counter containing the input bus. The Vi-bit shift register on the D-triggers and the element And, the inputs of which are connected to the inverse outputs of all bits of the shift register except the last, and the input of the first bit of the shift register is connected to the output of the element And, the input bus is connected to the clock inputs of all bits of the shift register, characterized in that, in order to shorten the exit time from the forbidden states, each bit of the shift register, except the last but one and the last, is entered the OR element, the output of which is connected to the installation input at the zero of this bit register and the shift, in each bit of the shift register, except for the first one, the inputs of the OR element are connected to the direct outputs of all subsequent bits of the shift register, the first discharge of which is the inputs of the OR element with & D with the direct outputs of all adjacent bits of the register shift, except for the last, the inputs of setting the zero of the penultimate and last bits of the shift register are connected respectively to the direct outputs of the last and first bits of the shift register. Sources of information taken into account during the examination 1. Elektroikka,, № 7, p. 55. 2. Gutnikov V.S. Integral electrotozh in measuring devices. L., Energie, 1974, p. 65, fig. 29 (prog) w).