SU866749A1 - Circular counter with device for detesting errors - Google Patents

Description

(54) RING COUNTER WITH DEVICE FOR DETECTING ERRORS

The invention relates to automation and computing techie and can be used in the implementation of technical tools in these areas. A ring counter with an error control is known, which contains a ring counter, two AND elements, two triggers, and an OR element l. A disadvantage of the known device is that it allows detecting mainly stable failures and the majority of Failures are not detected. The closest to the technical essence of the present invention is a ring counter with error control, containing an input bus, an N-bit shift register, two OR elements and an unequal element, whose inputs are connected to the outputs of the OR elements, the inputs of the first of which are connected to the direct outputs of the even bits of the shift register, the direct outputs of the odd bits of which are connected to the inputs of the second OR element, the input bus is connected to the clock inputs of the bits of the shift register, the direct output of the last bit and which is connected to the inlet of the first discharge shift register 2. However, the known device does not detect an error associated with the advent of spare units through an odd number of bits, and characterized by large apparaturnp 1 and costs. The purpose of the present invention is to increase the number of errors detected; To achieve this goal, a ring counter with an error detection device contains an input bus, an OR element and an N-shift shift register, the direct output of the last discharge of which is connected to the input of the first bit of the shift register, the clock inputs of which are connected to the input bus, An element is introduced, the inputs of which are connected respectively with the output of the element OR and with the direct output of the last bit of the shift register, the direct outputs to the last bits of which, by replacing the N-bit bit of the shift register, are united with the inputs of the element OR, where the number K is greater than or equal to the integer part of the number N / 2. .

The drawing shows a diagram of the proposed device.

The circuit contains N-bit shift register 1, bits 1 1 - shift register 1, the element OR 2, the element AND 3, the input bus 4 and the output bus 5.

The direct output of the last bit of shift register 1 is connected to the input of the first bit of shift register 1 and the first input of the AND 3 element, the second input of which is connected to the output of the OR 2 element, whose inputs are connected to the direct outputs of the last bits of the shift register 1 whose number is greater than or equal to the integer part of the number M | 2, the input bus 4 is connected to the clock inputs of the bits - the shift register 1.

Before starting operation, the counter is set to the state in which only one of its bits contains 1. When synchronization signals arrive on bus 4, the counter performs a cyclic shift of a single 1 in the field of its bits. When an error of the form of the number of units more than one after a certain number of input signals at the output of the element And 3 and there is 1, indicating an error.

From a comparison of this device with a known one, it can be seen that the depth of control of the present invention is substantially greater.

-Relative number of detected -n || g "g1 JMylH

errors M can be calculated by the formula

m

2N-1.

M is a little different from 1.

When

invention formula

An annular error meter counter containing an input bus, an OR element and an N-bit shift register, the direct output of the last bit of which is connected to the input of the first bit of the shift register, the clock inputs of the bits of which are connected to the input bus the fact that, in order to increase the number of detected errors, an AND element is entered into it, which is connected respectively to the output of the OR element and to the direct output of the last digit of the shift register, the direct outputs of which eliminating the N-ro bit of the shift register, connected to the inputs of the element OR, where the number K is greater than or equal to the integer part of the number N / 2. Sources of information taken into account during the examination

1. USSR author's certificate 416883, cl. H 03 K 21/34, 1974.

. 2. Sellers F. Methods of detecting errors in the operation of the digital computer, M., Mir, 1972, p.208, fig.11.7.

Claims (1)

Claim An annular counter with an error detection device comprising an input bus, an OR element, and an N-bit shift register. the direct output of the last bit of which is connected to the input of the first bit of the shift register, the clock inputs of the bits of which are connected to the input bus, characterized in that, in order to increase the number of detected errors, an AND element is inserted into it, the inputs of which are connected respectively to the output of the OR element and with the direct output of the last bit of the shift register, the direct outputs K of the last bits of which, with the exception of the Nth bit of the shift register, are connected to the inputs of the OR element, where the number K is greater than or equal to the integer part of the number and N / 2-