SU809167A1 - Device for comparing binary numbers - Google Patents

Description

(54) DEVICE FOR COMPARISON OF BINARY NUMBERS

and the third input of the second three-input element AND-NOT is connected to the device resolution bus.

The drawing shows a diagram of a device for comparing binary numbers.

The device contains an annular shift registers 1, the outputs of which are connected to the inputs of the binary Raman adder 2. The transfer output of the combinational adder 2 is connected to the inputs of the three-input and l -Aie.vienTOB AND-NOT 3 and 4, and the output su. ) | the combinational adder 2 is connected to the input of the three-input element AND-NO 3 and to the input of the two-input element AND-NOT 5. B1.1 of the input of the three-input control; 1-input of AND-NOT 3 is connected to the input of the three-input element AND-HE 4 and to the input of the two-input 9.1 elements AND-NOT O, B1,1 inputs of the elements AND-HE 4 and 5 are connected with 1 stroke of the two-input element AND-HE 6, nor-iiia 7 razravniy device is connected to the inputs of the three-input elements AND-HE 3 and 4.

The device works as follows.

When comparing the information of the three registers 1, I1inu rasrengeni 7 provides a single logical level. If units are written in the compared bits, the output of the sum and the non-transfer of adder 2 are single logical levels, and if the compared bits are zero, then the outputs of the sum and transfer of the adder 2 will be zero 1 logical level. If there are identical levels at the outputs of the sum and transfer of adder 2 at (5 output of the element AND-NOT 6, there will be zero potential, the signal of the equality of equalized bits. Iri inequality of the compared bits at the outputs of transfer transfer-adder 2; times; : 1O1 levels, and on B1, the input of the element IS-NE 6 will be a single potential signaling about the inequality of the bits to be compared.

When comparing the information of any two registers I from the specified three to the control bus 7 raster, a zero level is indicated, and zero information is written to the third register 1, which does not compare, and does not compare. If in the comparison bits of both registers of the Hi and i tangs or zeros, then the output of the sum of adder 2 will be zero logic level, and on B1) the input of the I-HE unit 6 is zero nogentiation, signaling about the equality of the bits being compared. If the analysis of the next bit revealed an inequality of information in them, then the output of the sum of adder 2 will be a single potential, and the output of the element AND-NOT 6 is a single level, indicating the inequality of the bits being compared. After the completion of the comparison of the next discharge, a shift pulse is applied to the advancing comparative numbers by one position. The number of shifts is equal to the number of bits of the numbers being compared and determines the full cycle of the comparison. Introduction to device combinational

an adder and two three-input elements Y-NOT allows to expand its functionality, makes it possible to compare the information of three consecutive codes or any two of the three specified ones.

Invention formulas

A device for comparing binary numbers, containing three ring shift registers, two two-input NAND elements, characterized in that, in order to extend the functionality due to the possibility of comparing three or any two of three consecutive codes, two three-input I-elements are entered into it NOT, and combinational adder, the inputs of which are connected to the outputs of the ring shift registers, and the output of the sum is connected to the first input of the first three-input element AND-NOT and to the first input of the first two-input element NAND, transfer output - from the first input of the second three-input element AND-NAND and from the second input of the first three-input element NAND, the output of which is connected to the second input of the second three-input element NAND and to the second input of the first two-input element NAND, the output of which is connected to one of the inputs of the second two-input element of the NAND, another input of the KOTOpoio is connected to the output of the second three-input element of the NAND, and the third input of the first three-input element of the NAND and the third input of the second three-input element of the NAND are connected to the bus p destructive device.

Sources of information taken into account in the examination

1. USSR author's certificate number 441560, cl. 2. G 06 F 7/04, 1974.

2. For Japan No. 4934367,

cl. 2 G 06 F 7/04, 1974 (prototype).

Zr and

Claims (1)

Claim A device for comparing binary numbers, containing three circular shifting registers, two two-input NAND elements, characterized in that, in order to expand functionality due to the possibility of comparing three or any two of three consecutive codes, two three-input elements And are introduced into it -NOTE, and a combinational adder, the inputs of which are connected to the outputs of the annular shift registers, and the output of the sum is connected to the first input of the first sin-input element AND-NOT and with the first input of the first two-input element AND-NOT, transfer output - with the first input of the second sineware element AND-NOT and with the second input of the first sineware element AND-NOT, the output of which is connected to the second input of the second three-input element AND-NOT and with the second input of the first two-input element AND-NOT, the output of which is connected to one of the inputs of the second two-input AND-NOT element, the other input of which is connected to the output of the second three-input AND-NOT element, the third input of the first three-input AND-NOT element and the third input of the second three-input AND-NOT connected to the bus device.