SU834926A1 - Counter testing device - Google Patents

Description

(54) DEVICE FOR MONITORING COUNTERS.

one

IeobreTerche is related to computing and can be used to monitor the performance of counting circuits.

A device for controlling the operability of the counter is known, which contains a matching circuit, a delay element, and triggers.

The disadvantage of this device is a relatively large monitoring time, the value of which depends on the size of the monitored counter.

Also known is a device for controlling a counter, which contains two coincidence elements and a delay element 2.

The principle of operation of the known device consists in checking the operability of the counter for an interval of time determined from the moment of installation in the counter of code K to the moment of installation of the code in it inverse K (k). If there were no failures (failures) in the counter for the specified time interval, then using the matching schemes, the values of the K and K codes are extracted at the required time points and a pulse of the correct operation of the counter is output. The amount of time control is determined by the counter

and, in the general case, it can be represented by the expression t 2, where t is the period of counting iguls, n is the size of the controlled counter.

A disadvantage of the known device is a relatively large time control. The aim of the invention is to reduce the monitoring time.

The goal is achieved

0 in that a device containing two elements of coincidence, the inputs of which are respectively connected to the inverse and direct outputs of the counter, is a delay element; three are entered

5 two-input elements And a differentiating circuit, with the output of the first double input element And connected to the input of the counter and connected through the delay element to the first

0 by the input of the second two-input element I, the second input of which through a differentiating circuit is connected to the direct output of the last digit of the counter, all inputs of the installation in the unit of which are connected to the output of the third two-input element I, the first input of which is connected to the output of the first element of the coincidence, and the second - with the input of the device, the output of the second coincidence element is connected to the first input of the first two-input element And, the second input of which is connected to the input of the device.

The drawing shows a diagram of a device for controlling a counter.

The device contains elements 1 and 2 of coincidence, a controlled counter 3, a delay element 4, two-input elements 5-7, a differentiating circuit 8.

The inputs of the match 1 are connected to the inverted outputs of counter 3, the forward outputs of which are connected to the inputs of the match 2.

The output of the double-input element And 5 is connected to the input of the counter 3 and through the delay element 4 to the first input of the two-input element Ib, the second input of which through the differentiating circuit 8 is connected to the direct output of the last discharge of the counter 3. All inputs of the installation into the unit of the counter 3 connected to the output of the two-input element And 7, the first input of which is connected to the output of the element

1 Matches. The second inputs of the two-input elements And 5 and 7 are connected to the input of the device. Item output

2 matches connected to the first input of the two-input element AND 5.

The device works as follows.

In order to monitor the operability of the counter 3, two control pulses are applied to the input of the device, the time interval between which is selected on the basis of ensuring reliable operation of the elements of the device when they are subjected to each of the specified control pulses.

Before operation, the counter 3 is reset to its original (zero) state, which is monitored by the coincidence element 1.

If the inverse outputs of all bits of counter 3 are 1, and the direct outputs are O (which indicates the initial state of counter 3), then the output of the coincidence element 1 is a signal that arrives at the input of element And 7 to ensure the passage pulse control. If counter 3 does not return to its original state (that is, after a certain time interval after the application of monitoring pulses), the output signal of the device 3 does not work at the output of the device.

The first control pulse passes through the element AND 7 to the inputs of the installation into the unit of the counter 3. Under the action of the indicated control pulse, all the bits of the counter 3 change their state to reversed, i.e. 1 appears on the direct outputs of the counter, which is controlled element 2 match. The signal from its output is fed to the input element And 5. to ensure the passage of the second control pulse. At the same time, the permitting signal, which came from the output of element 1, is removed, the coincidence signal to the input of element And 7.

The second control pulse passes through the element AND 5 to the input of the counter 3 and, being for the counter 3 an overflow pulse, returns

About all its bits to the original (zero) state. At the same time, at the direct output of the last discharge of the counter, a transfer pulse is formed, which through the differentiation circuit 8 enters the input of the element 6. At. another input of this element receives a second control pulse, delayed by element 4 for a time sufficient to form a pulse

0 transfer.

If counter 3 is healthy, then at the output of element b, a signal of correct operation of counter 3 is formed. The proposed device eliminates the dependence of the time of control on the bit of the controlled counter, which in turn reduces the time of control of the counter.

Claims (2)

1. USSR author's certificate No. 307522, class I 03 K 21/34, 1969. 2. Authors certificate of the USSR 5 219896, cl. G About F 11/00, 1968. la