SU822381A1 - Reversible decimal counter - Google Patents

Description

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The invention relates to the field of automation and computer technology and can be used in various areas of industrial equipment for counting the same type of input effects of any physical nature, for example, for counting the amount of production and its consumption, comparing two sequences of pulses, etc.;

The known reverse reversible counters contain a shift register, a character block, a correction block, a synchronization block, and two three-input binary adders 1.

Also known is a reverse decimal counter containing a synchronization block, a character block, a correction block, the first and second code reference blocks, the OR element and the shift register, the first output of the synchronization block is connected to the first input of the sign block, the second and third inputs of which are connected respectively to the summing the subtractive inputs of the reversible decimal counter, the first output of the correction unit is connected to the input of the shift register, the first input of the OR element is connected to the second output of the correction unit, the first input of which is connected to move the first block of code handling and to a fourth input of the block mark, which first output soe-. dinene with the first input of the second code conversion unit and the second input of the correction unit, the third input of which is connected to the second output of the synchronization unit and the first input of the first code conversion unit is connected to the output

0 shift register 2.

The disadvantage of these reverse decimal counters is the relatively low speed.

The aim of the invention is to increase speed.

The goal is achieved by the fact that in a reversible decimal counter containing a synchronization unit, a character unit, a correction unit,

0 the first and second code reference blocks, the | 1LI element and the shift register, the first output of the synchronization block is connected to the first bypass of the character block, the second and third inputs of which are connected respectively to the summing and subtracting inputs of the reversible decimal counter, the first output of the correction block is connected with shift register input, first element input

0 OR is connected to the second output of the correction unit, the first input of which is connected to the output of the first code inverter unit and to the fourth input of the sign unit, the first output of which is connected to the first input of the second code reversal unit and the second input of the correction unit, the third input of which is connected to the second output of the sync block, and the first input of the first code conversion block is connected to the output of the shift register, a trigger is entered, a direct output, which is connected to the second input of the first code inverter block, the output of which is connected to the second input the second block of code circulation, the second output of the block is connected to the second input of the OR element, the output of which is connected to the forward input of the trigger, the inverse input of which is connected to the output of the second code conversion block. The block diagram of the reversible decimal counter is shown in the drawing. The reversible decimal counter contains a synchronization block 1, a character block 2, a correction block 3, the first 4 and second 5 code reference blocks, an OR b and a trigger 7, and a shift register 8. The first output of the synchronization block 1 is connected to the first input of the sign 2 block the second and third inputs of which are connected respectively to the summation of 9 and the subtractive 10 inputs of the reversible decimal counter, the first output of the correction block 3 is connected to the input of the shift register 8 the first input of the element OR b is connected to the second output of the correction block 3, the first input of which It is connected to the output of the first code 4 unit and the fourth input of the sign 2 block, the first output of which is connected to the first input of the second code 5 block and the second input of the correction block 3, the third input of which is connected to the second output of the synchronization block 1, and the first code The first code 4 access block is connected to the output of the shift register 8, the direct output of the trigger. 7 is connected to the second input of the first code conversion unit 4, the output of which is connected to the second input of the code 5 reference block, the second output of the sign 2 block is connected to the second input of the OR element 6, the output of which is connected to the forward input of the trigger 7 inverse input which is connected to the output of the second block of code 5. The reversible decimal counter operates as follows. Synchronization unit 1 generates clock pulses, which are used as shift pulses of shift register 8, and synchronization unit 1 produces clock signals with frequency 4 on the first output - f -t J where f - frequency of clock signals / n - number of binary bits of shift register 8, and on the second output - synchronizing signals with frequency Ч 4 The number of binary bits of shift register 4 is selected according to the relation, where m is the number of decimal bits (tetrads) of the counter. Correction unit 3 is a shift register for two bits and, together with shift register 8, forms a sequential register for 4t bits. The character block 2 generates a signal on the first output that determines the operating mode of the reversible switch, (addition or subtraction), fixes the sign of the result and ensures the synchronization of the arrival of the counting pulses on the second output at the moments of reading the binary the decimal code is 8-4-2-1. In the initial state, trigger 7 is in the zero state and at its direct output operates a zero logic signal, in which the code 4 inverter passes without changing the serial binary-decimal code from the output of the shift register 8 to the first input of the correction block 3. Thus Thus, the binary-decimal code circulation circuit in a sequential register consisting of a correction block 3 and a shift register 8 is closed. The initial state of the counter is maintained until it arrives at a summing 9 or subtracting 10 inputs of a sequence of input pulses. In addition mode, the counter operates as follows. The character block 2 in the addition mode generates at the first output a zero signal, according to which the code 5 access block enters the transmission state in the direct signsshov code from its second input to the output, and the correction block 3 enters the state of a positive correction according to the forbidden code 1010. The first pulse of the counter, coming on the summing B24odod 9, is synchronized by the pulse of the first output of the synchronization unit 1 and is outputted by the second output of the character block 2. This pulse passes through the element OR 6 to the input of the trigger setup 7

and translates it into a single logical state by the time the low-order bit of the binary-decimal code is output from the output of the shift register 8. The transition of the trigger 7 to the single logical state leads to the switching of the code 4 inverter into the inversion mode of the sequential code arriving at its first input from the output of the register. shift 8.

The inverted binary-decimal code is sequentially, starting with the low-order bit, recorded from the output of the register shift 8 at its input through the code block 4 and the correction block 3 until trigger 7 returns to zero logic state and does not translate the code 4 access block into the transfer mode of the forward code coming from the output of the shift register 8.

The trigger 7 will reset the first unit of the inverted binary-decimal code to the zero state, starting with the low bit of the lower tetrad, which from the output of the access code 4 code passes without change through the address block code 5 to the inverted input of the trigger 7, and is also written to correction block 3.

The trigger 7 is set to the zero logical state after the first unit of the inverted binary-decimal code and transfers the code 4 reference block to the direct code transmission mode.

Thus, after the first unit in the inverted binary-decimal code, the remaining code bits from the output of the shift register 8 are transmitted by the code 4 reference block in the direct code, which leads to an increase in the binary code of the lower tetrad by one unit. .

Indeed, for example, the initial two-tetrad code was zero OOOO.OOOOOO. In its inverted code, the unit will be formed in the first bit of the lower tetrad, which is written to the register formed by the correction unit 3 and the shift register 8. The same bits of the initial binary - ten-code; - starting with the second bit of the lower tetrad, are rewritten without change, which results in the code 0000.0001 (one).

If, for example, a binary-decimal code 0000.0111 (seven) is read from the output of shift register 4, then in its inverted code the first unit is recorded in the fourth bit of the lower tetrad, after which the binary code of the second tetrad is rewritten in the forward code. As a result, a binary-decimal LLCO.OOO code (eight) will be generated.

Consequently, in the lower tetrade of the binary-decimal code, binary counting is carried out due to the control of the block reversing the code 4 by the signals of the direct output of the trigger 7.

Correction block 3 in the binary counting mode from O to 9 performs the function of a shift register by two bits, additionally the shift register 8 to 4t bits.

The tenth input pulse acting on the summing input-9 will change the state of the lower tetrad to the forbidden lOlO code, on which the block is triggered, of the correction 3 on the fourth-bit clock signal coming from the second output of the sync unit 1 to the third

The 5 input of the correction block Z. The correction block 3, in the summation mode, forms, on code 1010 at its second output, a signal that closes the shift circuit for one measure in the correction block 3, erasing the units in the second and

the fourth bit of the lower tetrad, the correction signal from the second output of the correction block 3 is supplied through the element OR b to the direct input of the trigger 7, it is set to one

5 state, which leads to the transition of the code conversion unit 4 to the inversion mode by the moment of reading the low-order bit of the second tetrad from the output of the shift register 8. Thus

0

the binary count is being transferred to the second tetrad, in which the pre- code generation is carried out similarly to the code conversion described above in the first tetrad.

5, as a result, after ten input pulses in the summation mode, a binary-decimal code is formed. 0001.0000 (ten).

Further binary counting in tetraQ dah and decimal counting from the lower tetrad to the highest in the summation mode is carried out in a similar way.

In subtraction mode, the counter operates as follows. .

 The block of character 2 in the subtraction mode generates at the first output a single logical signal, according to which the block of code 5 turns into the inverted state of signals

0 arriving at his second entrance with

the output of the code circulation unit 4. In addition, a single logical signal of the first output of the block of character 2 is supplied to the second input of the correction unit

5 3 and translates it to the negative correction state using forbidden code 1111.

The input pulse of the counter, arriving at subtractive input 10, is synchronized by the pulse of the first output of synchronization unit 1 and is output to the second output of the character block 2. This pulse passes through the OR element b to the setup input of the trigger

5 7 and translates it into a single logical state by the moment of reading the low-order bit of the binary-decimal code from the output of the shift register 8 The transition of the trigger 7 to the single logical state causes the code 4 to be switched to the inversion mode of the sequential code arriving at its first time G output shift register 8.

The inverted binary-decimal code is sequentially, starting at the low-order bit, written from the output of the shift register 8 to its input through the code conversion block 4 and the correction block 3 until the trigger 7 returns zero logic and transforms the block Code 4 is converted to the direct code transfer mode, coming from the output of the shift register 8.,

The trigger 7 will return to zero logic the first zero of the inverted binary decimal code, starting with the low bit of the small branch of the tetrad, which from the output of the code 4 inverter enters the second input of the code 5 inverter, where it is inverted into a single logic signal trigger reset input7.

The trigger 7 is set to a zero logic state after the first zero of the inverted binary binary code and switches the code reference unit to the forward code transmission mode.

Thus, after the first zero in the inverted binary-decimal code, the rest of its bits are transmitted to the blocks of the return code 5 in the forward code, which leads to a decrease in the lower tetrad by one unit.

Indeed, if, for example, the output of the shift register 8 reads the binary-decimal code 0000.1000 (eight), then in its inverted code the first zero is formed in the fourth bit of the lower tetrad, after the second binary the code of the second tetrad is rewritten into code. As a result, a binary number 000.0111 (seven) is generated.

Therefore, a binary subtraction is performed in the junior tetrad of the binary-decimal code by controlling the code 4 access block from the side of the trigger 7.

Correction block 3 in the binary subtraction mode from 9 to O performs the functions of the shift register by two bits, in addition to the shift register to 4 bits.

The counting transition from the tetrad to the tetrad in the subtraction mode is carried out as follows. If, for example, a binary-dec is read from the output of shift register 8, the personal code 0001.0000 (ten) and the input pulse 10 acts on the subtracting input 10

which sets trigger 7 to a single state, then trigger 7 will retain this state during the inversion of the code 4 of all bits and bits in the inverter; of the tetrade, in which the forbidden code 1111 is formed.

The correction unit 3 in the subtraction mode is triggered by the forbidden code 1111 and closes one shift circuit in the correction unit 3 by erasing the units in the second and third digits of the lower tetrad. This converts the forbidden code 1111 of the lower tetrad to binary code 1001 (nine).

Since the first zero in the inverted binary-decimal code 1110.1111 is generated by the code 4 reference block only in the first bit of the second tetrad, the trigger 7 returns to the zero logic state after the first bit of the second tetrad and switches the code 4 block to the forward code transmission mode .

As a result, instead of the source code 0001.0000 (ten), the new binary-decimal code 0000.100Q1 (nine) is written to the shift register 8 from the output of correction block 3.

Further binary subtraction in tetrad and the decimal transition of the count from the lower tetrad to the older to the subtraction mode is carried out in a similar way.

If, in the subtraction mode, in all tetrads of a binary-decimal code on the output of the block of code 4 code reversal), a zero code is inputted to subtractive input 10, an input pulse arrives, then the character 2 block is triggered by signals from the code 4 block to its fourth input , which leads to a change in the sign of the result to a negative and translates the counters in the summation mode.

If the sign of the result is negative and the input pulse arrives at the summing input 9, then the sign 2 block translates the counter into the subtraction mode

If the sign of the result is negative in all tetrads of the binary-decimal code, a zero code is formed at the output of code 5 block, and an input pulse arrives at summing input 9, and the sign 2 block changes the sign of the result to positive and puts the counter into the summation mode.

In this way, a decimal count is made with both positive and negative numbers.

The absolute value of the counting result is recorded in the binary-decimal code 8-4-2-1 in the sequential register, which is formed by the connection of the correction block 3 and the shift register 8. The counting result symbol is fixed by the sign 2 block.

Claims (2)

Claim A reversible decimal counter, containing a synchronization block, a sign block, a correction block, the first and second code access blocks, an element. OR and a shift register, with the first output of the synchronization block 'connected to the first input of the sign block, the second and third inputs, which are connected respectively to the summing and ON-OFF,: with the input inputs of the reversible decimal *, th counter, the first output of the correction block is connected to the input shift register, the first input of the element, OR is connected to the second output of the correction unit, the first input of which is connected 1 to the output of the first code block and the fourth input of the sign block, the first output of which is connected to the first input of the second block the ode and the second input of the correction unit, the second third input of which is connected to the second output of the synchronization unit, and the first input of the first code reversal unit is connected to the output of the shift register, characterized in that, in order to improve performance, a trigger is inserted into it, the direct output of which connected to the second input of the first block of code reversal, the output of which is connected to the second input of the second block of code reversal, the second output of the sign block is connected to the second input of the OR element, the output of which is connected to the direct input of the trigger, the inverse input to The second is connected to the output of the second block of code reversal. 5 Sources of information taken into account during the examination, 1. '· Computer technology ¹ ·, t.11, Energy, M.-L., 1964, p.354. 2. USSR author's certificate No. 374643, cl. H 03 K 27/00, 1971 (prototype).