SU794753A1 - Device for transmitting and receiving discrete information through variable-length parallel communication channels - Google Patents

Description

In addition, on the receiving side there is a read address counter, a clock selection unit and a second memory block, while on the transmitting side the installation output of the control unit is connected to the installation inputs of the sensor of the marking combination, the input of which is connected to the generator input of the recurrent sequence, allowing the input connected to the permissive output of the control unit; the generator output of the recurrent village of the subcontrol is connected to the service input of the switch; on the receiving side, the input of the first switchboard one of the inputs of the first memory block, the record input, the read input and the control input of which are connected respectively to the output of the first write address counter, to the output of the address counter c; read and to the read input of the second memory block and to the third output of the control block , the first and second setting inputs of which are connected to the output of the first and the output of the second decoder, the fourth, and the scattering outputs of the control unit are connected respectively to the control input of the clock selection unit, the control input of the second of the memory block and the control input of the read address counter, the clock input of which is connected to the clock output of the clock selection block, which is connected via a valve to the clock input of the sampling circuit, another information input of which is connected to the output of the second memory block, the write input and another input which are connected respectively to the output of the second counter of the write address and to the input of the second decoder, and the input of the first decipher is the first information input of the receiving side, and the input of the second decoder ra - a second data input.

The drawing shows a structural electrical circuit of the proposed device.

The device contains the distributor 1, the control unit 2, the sensor 3 of the marking combination, the switch 4, the recurrent sequence generator 5 on the transmitting side, the first 6 and second 7 decoders, respectively the first 8 and second 9 write address counters, respectively, block 10 on the receiving side control, the first memory block 11, the distributor 12, the sampling circuit 13, the second memory block 14, the read address counter 15, the clock selection block 16, the information signal being transmitted to the switch on the switch and the input on the receiving side The first decoder is the first information input, and the input of the second descrambler is the second information input.

The device works as follows.

On the transmission side, information from the message source is fed to the information input of the switch 4, which, but to the control signals from block 2, connects to the communication channels either information (in information transfer mode) or recurrent continuity of sensor 3 or generator 5 ( in phasing mode).

Sensor 3 doesn’t / itself represent a recurrent sequence generator, which, according to signals from block 2, sends to the switch 4 phase locking or phase loops formed as different from each other fixed lengths of the length of the recurrent sequence of length L of the noise-tolerant reception conditions and, as a rule, a multiple of the distributor 1 cycle. In addition, at least n / 1 + 1 segments of length m should be placed on the length of length n, where m is the number of bits equal to the degree of the half-length recurrent preferably (ktn of length V, a / g (1, 1 ... k)) depends on the grouping of errors in the communication channel.

Generator 5 of the recurrent sequence — a register with feedback — supplies the switch 4 with the current values of the recurrent sequence of length M, carried out by it, which is bitwise numbered from the incoming information.

In order to carry out the bit-wise numbering, on the transmission and the possibility of its restoration at the reception, it is necessary to correctly select the degree r of the generating polynomial of the recurrent sequence of the generator 5. The choice should be made taking into account the maximum possible propagation time in the channels and the transmission rate. Below is a practical formula for choosing the degree of the generating polynomial of the recurrent sequence of the generator o.

(1 ,, „SW.1

In

g

1p2

1De / Shahdlin

maximum possible

channels;

WITH

- the speed of light; is the time determined by the delayed information on the instructions (m d 1.5, where d is the number of perepriem, 1.5 is the average information delay time of the perepim, ms); B - the speed of information transfer in the channel.

The selected length of the recurrent sequence M - 2 -1 corresponds to the maximum possible difference in propagation time in the channels, expressed in information bits.

In operation mode, generator 5 performs bit-wise numbering of information synchronously and in-phase across all channels. The bit numbers are not transmitted to the communication channels. In the phasing mode, the transmission of the current length segment, the recurrent sequence M, independently in each channel synchronizes the counters 8 and 9 on the receiving side.

When synchronization is lost in the channel, cyclic phasing and recovery of message addressing (bit numbering) is performed as follows. The side that detected the loss of synchronization inserts a length of the length n of the recurrent sequence L of sensor 3 (the combination Phase Request) and, after it, sends the segment Y to another recurrent sequence M (the current value of the generator 5). The length of the segment Y of the recurrent sequence M of the generator 5 is selected from the condition of reception noise immunity, provided that this segment is always transmitted after the marker and this ensures its noise immunity. The length of the segment, for example, can be chosen equal to the cycle of transmitted information. However, in the general case, to determine the length of the segment y, it is necessary to know the statistics of grouping errors in the communication channel. At the same time, in order to reliably pass the synchronizing signal, it is necessary to choose its length greater than the average number of bits between the edges of the noise spikes.

Thus, the first of the phasing combinations is a marker, it is used for cycle synchronization, and the second is the adjustment of the counter, which restores the bitwise numbering at the reception. The party that receives the “Phase Request” combination, in response, sends the “Phase” marker and, after it, a segment of the recurrent sequence M.

On the receiving side, the device operates as follows.

The decoder 6 (or 7) searches for a segment of the recurrent sequence of length / n. Separating it from the received information, it forms a reference recurrent sequence, the subsequent characters of which are the continuation of the selected segment, which is estimated as the first of the k segments of length m. At the same time, the length segment l of the phasing combination begins, taking into account that one of its length m Each of the subsequent selected segments of the recurrent sequence is compared with the corresponding segment of the reference sequence, and if k such segments coincide, the resolution selection from the reference sequence of the segment /, which is the last segment of length m on the segment of length p. The presence of an error between the selected segments of the recurrent sequence of length m does not affect the performance of criterion k if each subsequent selected segment coincides with the corresponding segment of the reference sequence.

Selecting a segment / within the segment of the length of the transferred marker completes the search

marker "Request phase or" Phase.

The mismatch of the next selected segment with the corresponding segment of the reference sequence, if the criterion k is not fulfilled, leads to a repetition of the search for a marker. The formation of the reference sequence, the counting of the length of the marker p and the accumulation of k begins with a mismatched segment of the recurrent sequence.

If the criterion k is developed, then the mismatch of the next selected segment with the corresponding segment of the reference sequence does not affect the sequence of operations for receiving the marker.

Such a noise-tolerant reception of the marker makes it possible to receive not only the marker itself, but also a combination (the current value of the recurrent generator 5 sequence) to adjust the counters 8 (or

9) write addresses.

After receiving the marker, the decoder 6 (or 7) allows reception of information from the channel to counter 8 (or 9) of the write address, which is the receiver of the recurrent sequence M (register with feedback). After receiving the current segment v of the recurrent sequence M, the counter 8 (or 9) gives permission to record information in block 11

(or 14), which is a random access address storage device (RAM), disconnects from the channel and goes into the sensor mode of the recurrent sequence of length M and repeats with a shift by the propagation time in this channel, the sequence of the generator 5 of the recurrent sequence, restoring bitwise numbering information at the reception. Consequently, after the end of the phasing mode in both channels, the counters 8 and 9 of the write addresses are shifted by the difference in the propagation time of the channels and they are controlled by writing the same information bits to the same addresses of blocks 11 and 14.

Information is read from both memory blocks simultaneously using a counter 15, which is a feedback register, forming a recurrent sequence of the same length as generator 5, and shifted in time to the side of the sequence of the first of the phased counters 8 ( or 9).

Consider in more detail the process

Starting the counter 15. After turning on the power of the equipment, both channels switch to the cycle phasing mode. At the same time, unit 10 controls the counter 15. The first of the phased channels (as a rule, shorter) outputs to the control input of unit 10 a signal on which unit 10 performs the following operations:

parallel rewrites the current value of the phased counter 8 (or 9) into the counter 15;

for block 16, for the maximum possible difference in propagation time, a tick inhibit signal is sent to counter 15;

after the time the maximum possible difference in propagation time between the channels allows the passage of the first of the phased channels to the counter 15.

After these operations have been completed, block 10 is blocked (counter 15 is not controlled), counter 15 simultaneously reads the information bits of the same name from blocks 11 and

14 with a delay of M bits regarding the reception of information by the first of the phased channels.

Thus, in the mode of simultaneous phasing of both channels, the counter 15 is started, the operation of which later remains immeasurable until the next moment of its simultaneous phasing. Selection of the counter operation cycles

15 and the distributor 12 is carried out by a block 16, which, by means of control signals, performs continuous switching of the clock of the de-phased channel to the steps of the phased channel. From the above it can be seen that the process of temporal alignment of channels occurs only with simultaneous phasing in both channels. The information from blocks 11 and 14 is fed to the circuit 13 and with the read cycles provided to the subscriber from the channel where there are currently no errors.

Storage units (matrix) of matrix type with address selection can be selected as memory blocks. Such a memory contains an infurmation input and output, as well as clock and address inputs. The received information sequence is fed to the information input, the corresponding channel clock is applied to the clock input, and the current state of the counter 8 (or 9) is fed to the address inputs in parallel. At the same time, information is entered into the memory unit cell corresponding to the specified address of the entry. The write addresses change sequentially from 1st to 7th, and the received information is sequentially recorded in the first, second, ... seventh cell of the memory block. Information from block 11 (or 14) is read when the current state of counter 15 is fed to the address inputs of both memory blocks, and information is output from the information output of block 11 (or 14) (from memory cells corresponding to the given read addresses). For example, at time ti, the information bit "a is written into the first cell of the memory, and at time / 2

this bit is issued from this memory. The snoring time (delay) of the information is 3 bits.

Thus, when using an address storage device as memory blocks, the same information from both channels at different times fits into the same cells of blocks 11 and 14, and is read from these memory blocks simultaneously, while the delay

the information in block 11 (time interval) is greater than the delay in information in block 14 (time interval tz- / 2), since the first channel is shorter than the second channel. At the time point, the first channel failed,

information on it is not received until time s, and this channel has changed its length as a result of the reservation. Counter 8 of the first channel restores bitwise after reservation

numbering in this channel and corrects the delay in the information of the first channel (block 11). At the same time, the first received information bit after reservation is delayed by a segment

time, less than the delay time of information on the second channel, as a result of the reservation, the ratio of the lengths of the channels changed, and the first channel became longer than the second.

A significant feature of the satellite channel is the change in the frequency of received information due to the Doppler effect. Over a period of time, an increase in frequency occurs, which occurs when a satellite approaches the Earth. At time 14, the satellite is replaced, and from time, the frequency of the received information (the satellite moves away from the Earth) decreases.

Thus, the introduction of new units with their connections in the proposed device made it possible to eliminate the shortcomings of the prototype and, consequently, improve the reliability of information transmission when working with uncontrollable sources of information over variable length channels.

Claims (1)

1. Shl pobersky V.I. Fundamentals of the technique of transmission of discrete messages, M., “Sv z, 1973, p. 437-440 (prototype). INF