SU1406806A1 - Discrete information transmission system - Google Patents

Abstract

The invention relates to telecommunications. The purpose of the invention is to improve noise immunity. The system contains on the transmitting side of Mr. 1 clock pulses, EL-OR 2, RS-flip-flops 3 and 5, the address setting block 4, multiplexer 6, shift register 7., modulator block 8 two, the decoder 9 zero combination, digital comparator 10 and driver 11 pulses, and on the receiving side - the regenerator 12 of the input signal, rr. 13 clocks, multiplex

Description

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(4 15 2 --g registers

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edBy GE5 3Jr-T and 17, counters 18, 25 and 31 Pu-inyjLbcoB 3 B.5 - trigger 19 and 23, jji-i Di ShZh 20 and 21, address setting block 22, db. coder 27 d.ch. HKtjwpMauiHH, block adders

24 and adder 30 modulo two, Pel is achieved by providing the BOZ with the ability to generate the M-sequence with cyclic shift AND for address transmission of discrete information, 1 or и

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The invention relates to telecommunications and can be used in systems for session transmission of discrete information.

The purpose of the invention is to improve the noise immunity,

The drawing shows a structural, electrical circuit of a discrete information transmission system.

The discrete information transmission system contains on the transmitting side a generator of 1 clock pulses, an OR 2 element, an RS-flip-flop 3, an address setting block 4, an additional RS-l P ngg ep-5 3 multiplexor b, a 7 PASH register .- :, J, a block 8 with; {matte by fashion kombir1; ; a T :: W / l 1: a., c -B j and at the receiving CToposf serge neun op i2 of the input CHi HaiiA, yy;:; - 1 lzzor l3 TSKTcat x km –pool & eoE, i epBbrti multilehsor 14. the first 15 L second reg istry shift, zlekek: and 17., the first counter of 13 pulses, Lergash RS-TpFiri ep 9, the first 20 and the second 21 CLI, block 22 installed health, RS second Tpi T G r 23, the second multiplexer 24, this is V Oji counter 25 I1 p1ull oz, block; 25 i; j: t04efij desh: 1frator 27 ohochchmtn transmissions of 1Station, registration p: - S with modulo 29 cji .iMaTopoti modulo two g. l-gator 30 about modulk two and;: with- full account IR: 31 h17.pulsoE,

In the drawing of the convoy Gachen kan ;; l.; 2

System per - 11; .ychi diskre, tysy 1-sh formation.. Slyduto-EGM way

B i icxoAtsoM soss, on the line 1La transmitting side RS-trkgl er 3 kaquarkan signal signal y;: k ;; vd. this; In spite of Ny, the presence of signals from generator i on ta1; goblin E:, GSde register

a record

sg; wig sig

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 no bits occur in it. All bits of the register 7 are in the zero state, which provides a level 1 signal at the output of the decoder 9 and, therefore, the inclusion of register 7 in the parallel information recording mode at the control input. Signals of additional RS-trigger 5 switching of transmission modes including channels X | - X multiplexer 6, which provides connection to the input of channel 32, communication its second bit of the first information inputs of the multiplexer 6 and to the input of the serial recording of register 7 according to the output of the output of block 8 of adders and the transmission But parallel, 1Y parallel register recording 7 and the first information Digital comparator 10 signals with df / od of address setting unit 4. With this signal; The output of the digital comparator 10.J corresponds to the last element of the M-sequence, which is formed by clock-by-1 pulses from generator 1 of rugby 7 to block 8 of adders.

Upon receipt of a kk signal of level r to the 3 input of RS - TpHr epa 3, the latter switches to another state. In perviCi p 7 production. the recording of signals from the block 4 of the address addressing, the result of the signal 1 and 1 of the decoder 9 disappears and, as a result, regx-7 translates- ::: ;; C 1; consecutive record y. :; dvng ak; {formations. Under the action of; sp pulses register 1 and block; -,:. : l-gmatorsv forms - elements of M-s: scoops; that raio v 3 communication channel. By setting the initial state of register 7, the shift, e, by writing and breaking it, and signal- Jioa with b, lo} Ci 4 settings addressed; |, o1-tpg, -and.pch; ns mm (.. geerno-russia m-loc.schedopnost with cyclic shifts, h G about provides n; ipf cnyio transfer of discrete information, Formation and transfer zlemeiton M- | 1sext;) D) .III, POST dptpts tsr the moment of coincidence of the signals at the second and first information inputs of the digital comparator 10 on the last element of the M-sequence.

The imaging unit 11 ensures the separation of the decay of the pulse arriving at its input from the digital comparator 10 after the formation and transmission of all elements of the M-sequence. Under the action of a signal from the output of the imaging unit 11, the RS flip-flop 5 turns on the Y channels and turns off the X channels of the multiplexer 6, which provides information transfer mode, and the register 7 is zeroed, which ensures the setting of the parallel recording mode. The signal of the shaper 11 in length is much less than the clock interval of the oscillator 1, therefore the next pulse from the oscillator 1 records the bits of the register 7 signals arriving through the channels Y of the multiplexer 6.

After recording the signals in register 7, it enters the M-sequence generation mode with initial conditions determined by the values of the signals of the transmitted information. Due to the inclusion of the Y channels of the multiplexer 6, the serial record of the register 7 is connected, the input of the communication channel 32 and the additional first information input (which is the low-order input for the first information inputs) of the digital comparator 10 of the corresponding output of the adders block 8. Due to this, information is transmitted due to cyclic shifts of the second, different from the first M-sequence (which provides an additional increase in noise immunity). The transmission of the second M-sequence also lasts until the first and second information inputs of the digital comparator 10 establish equality of signals, which will occur as in the described case of transmitting the first M-sequence, only on the last element of the M-sequence. After transmitting the BTOpoii M-sequence

0

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five

0

five

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the shaper 11 generates a signal 110 to which a new value of the transmitted information signals is established at the information input of the discrete information transmission system, by which a new value of the initial state of register 7 is established, which ensures the transmission of the M-sequence of the second type with a new cyclic shift. In the absence of transmitted information on the signal (Request for information on transmission) of the former 11, the third information inputs of multiplexer 6 are set to a combination of the transmission of information, after transmitting which the short-term signal arrives at the input of the transmission of information from the discrete information transmission system and sets the RS-flip-flop 3 in the initial state. Setting the RS flip-flop 3 to the initial state results in a level 1 signal at its inverse output, which sets the initial state on the transmitting side and stops transmitting.

When a transfer is resumed, the processes proceed in the order described.

Receiving information in the discrete-information transmission system occurs as follows. In the initial state, on the receiving side, the first 19 and second 23 RS-flip-flops on their inverse outputs have a level-1 signal. This signal from the inverse output of the first RS-flip-flop 10 sets and holds to zero state by R-inputs the first counter 18 and the second register 16. The signal from the inverse output of the second RS flip-flop 23 establishes and holds in the zero state the second counter 25 and turns on the channel: n, 1 X the second multiplexer 24, through which Accordingly, the connection of the information inputs of the parallel recording of the third register 28 to the corresponding outputs of the address setting block 22, the connection of the input of the sequential recording of the third register 28 and the second input of the adder 30 to the first input of the block 29 of the adders, and the night of the first input of the adder 30 to the output of the last bit yes first register 15.

The transmitted signals from channel 32 of the transmitted signals are sent to the pegener i op sij which is regenerated by r rix using clock No. 1 pulses Generator – TO ija 13 with the frequency of the pulse of the transmitting side generator 1 at least in the number of elements, constituting one M-sequence. time. Regenerated signal gustep; t from the information output of the regenerator 12 to the input of the Y channel of the first multiplexer .14,

The values of each element (bit) of the received sequence are recorded in the first register 15, which is accomplished by turning on the Y channel of the first multiplexer 14 according to the signal from the clock output of the peer generator 12 supplied to the control input of the first multiplexer 14 Nor is one period of the oscillator signal 13. During the remaining 5 clock cycles per bit of the received sequence, the input of the sequential recording of the first register 15 is connected via channel Y of the first multiplexer 14 to s for the final output of the last bit. The number of times the rows of register 28 is equal to the number of elements M-sequential.

To the reception segment pos ;; e, tsne: o ele- le M-tyaleneledukopti E first poi rfcTpe 15 having turned out; AKTs recorded all 1; : -chie bits of the received M follower-just. At each bit of the received M-trainJJno .. it writes 28 bits of initial conditions into the bits of the third register 28 specified by the address setting unit 22. To ensure /. receiving information carried bhoj a 1-g; -,:; To the initialness of the initial yf .jiOBHKj given by the address setting blocks 4 and 22. The recording of the ground conditions in the third region / 8 provides 1 With the supply of signals from the outputs of the address setting unit 22 through the corresponding channels X BTCipc multiplexer 23 ka. the inputs of d B of the third re, - and with tp a 28, y with. t a; (a s - limeoge for the duration of the clock; -; o r 13; re; kim aara,) le1P; stop recording, by giving a signal from the res output from the oscillator 12 and the input to control the recording mode of the register 28, thus, on each bit The M-sequence is provided by: on the record in the first register 15 sria-- the follower is

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, V tre7 I11 pLM HC ip 28 of initial conditions (hell, resale) conditions and resetting the preheater counter 31, Under the influence of the remaining clock pulses of the generator 13, received for a long time (in a first register, 15 overwriting information.

ig of the last bit of the first register 15 values of the recorded bits of the M-sequence are received via the corresponding channel X of the second multiplexer 24 to the adder 30. Under the same pulses, the third register 28 provides the formation of the elements of the reference M-sequence identical to the transmitted .

The standard M-sequences of the 2Q are fed to the adder 30 for comparison with the MIT bit stored and recorded in the first register of the 15 M-sequence. At coincidence of values of the compared it is accepted. and the TJT lonor P of M-sequences and the shift of the elements of the received M-sequence, the number recorded in the additional counter 31, is equal to the number of coincidences of the elements of the received and reference M-sequence. If all the bits of the transmitted M-sequence are received and their permissible distortion occurs, then at the last tick of the M-sequence when performing;

35, the counter 31 generates a signal that arrives at the S-input of the second RS-flip-flop 23 and switches its output. The output signals of the second RS-flip-flop 23 allow the second counter 25 to operate and include the corresponding channel Y of the second multiplexer 24, through which the inputs of the bits of the third register 28 are connected to the corresponding outputs of the bits of the n-th counter 18, ikfos. The math input is from the second record, the horn 23 and the second input of the sutmator 30 sc / shchats to the second output of the block 29 of adders, left input of adder

50 30 is connected to the output of the last bit in the mountains of the register 16.

.Hial H: J output of the second ticker:.; t, o c) through the period i i; incompatibility - ;. This signal is equal to

4S O;. Ai: -unality of the hegerator cycle 13, g.k L uische - lia S-iixon, the first short-circuit trigger 19 and Bxo; i y ;; the recording mode BTopoi o reg h rstrn 16. Signals

thirty

40

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From the first output of the first E S-trigger 19, the first counter 18, the second register 16 are allowed to operate, and the signals pass through an AND 17 element. The second pei 16 also records information accumulated in the first register 15 during the interval of the second counter 25. The first counter 18 of the operation performs the counting of signals from the clock output of the regenerator 12, which sets the third register 28 to parallel recording mode.

The signals from the output of the bits of the first counter 18 are recorded per clock from the generator 13, and then the elements of the second M-sequence are formed from the recorded signals of the initial conditions. The formation of the second M-sequence, identical to that transmitted, is provided by the corresponding output signal of block 29 of adders, identical to block 8 of adders of the transmitting side. Since, at each clock cycle, the signals at the outputs of the bits of the first counter 18 change, the initial conditions from which the M-sequence is formed from clock to clock (from bit to bit) also change. The formation of the elements of the M-sequence is accompanied by a comparison in cyt-iMaTope of 30 of their values with the values of the elements of the received and recorded in the second register 16 of the M-sequence. When ycTanoBJieiiHoro coincides with the number of sequence elements, additional counter 31 has time for the bit interval — overflow from the clock pulses of the generator 13. This signal indicates that the 16 M-sequence on the transmitting side was formed with identical initial conditions set first counter 18 for this revision. The signal from the output of the additional counter 31 is fed through the element AND 17 to the output Permission to receive information from the discrete information transmission system, to the first input of the second element OR 21 and to the control input of the key block 26.

The signals from the outputs of the bits of the first counter 18 through the corresponding channels X of the second multiplexer 24 and the block 26 of the keys are fed to informational outputs of the transmission system e1-hidden information. With vkoda vto680ft8

poi o power io 21 or the signal arrives at the R input of the first RS flip-flop 10 l sets it to the initial state, setting and keeping in the initial state the first counter 18 and the second register 6. After the end of the period of the next M-sequence the signal at the output of the second counter 25 and the described verification processes are repeated. If at reception there were errors in the elements of the M-sequence above the established norm, then the first counter 18 for the period

g M-sequences do not null and overflow. The overflow signal through the first 20 and second 11 elements OR sets the first 19 and second 23 RS-flip-flops to the initial state,

Q which causes the entire receiver side to be reset. The end of reception of information in the presence of reception of all M-sequences is performed by deciphering the combination of the end of the transmission of information by the decoder 27 and setting it with the signal of the first 19 and second 23 RS-triggers to their initial state through the first element of the ShSh 20..

Claims (1)

Invention Formula A discrete information transmission system containing serially connected shift registers and a digital comparator on the transmitting side, as well as a clock pulse generator, an RS flip-flop and an OR element, on the receiver side — a serially connected clock pulse generator, input-signal regenerator, first pulse counter and the first EL, the second counter of 11 pulses, the clock input of which is connected to the clock output of the input regenerator five 0 the signal, a series-connected element AND, a block of bits and a decoder of the combination of the end of the transmission of information, the output of which is connected to the second input of the first element OR, 0 as well as the first RS trigger, the inverse output of which is connected to the setup input of the first pulse counter, the second RS trigger and the second element j-SHI, and the output element 5 And the outputs of the key block are the output, respectively. Permission to receive information and information. System outputs, of which it is | h, h. 4 so that, with the help of the system, € 11CHN1) ps-ti, on the transmit side, iiocnejj, oBaTejrb- but connected adder unit modulo dng1 and multiplexer are entered, and the address setting block, whose outputs are connected to the second information inputs of the multiplexer, the zero-combination decoder, the zero combination, outputs and output connected respectively to the corresponding outputs of the shift register and the control input of the write register of the shift register, the additional RS trigger, the forward and inverse outputs of which are connected to the corresponding control inputs of the multiplexer, the pulse driver, the input and output of which are connected respectively to the output of the digital comparator and the combined S-input of the additional RS- trigger and the first input of the OR element, while the second input of the OR element is combined with the R-input of the additional RS-flip-flop and connected to the inverse output of the RS-flip-flop, the outputs of the OR element and the clock pulse generator Ls are connected respectively to the installation and clock inputs of the shift register, the information input of the sequential recording of which is combined with the additional first information input of the digital comparator and connected to the first output of the multiplexer, the second outputs of which are connected to the corresponding information inputs of the parallel recording of the shift register and the second information inputs of the digital comparator, the outputs of the shift register are connected to the corresponding inputs of the modulo adders block two, and The S-input of the additional RS-flip-flop, the S-input and the R-input of the RS-flip-flop, the third information inputs and the first output of the multiplexer are respectively the input Transmission information request, Transmission start input, Information transfer end, in (}) form - at the receiving side, inputting the first multiplexer, the first and the second shift registers, the clock inputs of which are connected to the output of the clock generator, and the second multiplexer, are in series th shift register and block sum 0 five 0 five 0 five 0 And rop 1b1 Mo / tyjno, ergplj and ptorg.yylo; C 1 of which lods () to the corresponding first and informat.iomnymi inputs of the second multiplexer, serially connected modulator of two and an additional pulse counter, the clock input and output of which are connected to the output of the clock generator and the combined S-input of the second RS-flip-flop and the first input of the element I, while the input controlling the recording mode of the second shift register is combined with the S-input of the first RS-flip-flop and connected to the output of the second pulse counter, The tuning input of which is combined with the first control input of the second multiplexer and connected to the inverse output of the second RS flip-flop, the direct output of which is connected to the second control input of the second multiplexer, the setting input of the second shift register is connected to the inverse output of the first RS-trigger, R- the input and direct output of which are connected respectively to the output of the second element OR and the second input of the element AND, the output of the second shift register and the auxiliary output of the first shift register are connected but to the information input of the sequential recording of the second shift register and the first information input of the first multiplexer, the second information and control inputs of which are connected respectively to the information and clock outputs of the input regenerator, the additional shift of the first shift register and the output of the second shift register are connected to the corresponding second information - the main inputs of the second multiplexer, the third and fourth information inputs of which are connected respectively to the current outputs of the address setting block and the corresponding bits of the first pulse counter, the outputs of the key block are connected to the corresponding outputs of the second multiplexer, the first and second additional outputs of which are connected respectively to the first input of the modulo two adder and the combined information input of the third register shift and the second input modulo two, the output element 1 i -1- 1068061 2 And connected to the first input is second connected to the mode control input element OR, the second entry of the third shift register and go combined with the R-input of the second RS-installation input additional trigger and connected to the output of the pen-pulse counter, clock input element OR, the clock output of which is connected to the output of the generator of the input signal of the sub-clock clock pulses.