SU1177932A1 - Receiver of cycle clocking signals - Google Patents

Description

The invention relates to multi-channel communication systems with time division multiplexing, in particular to frame alignment receivers, and can be used in digital information transmission systems for rural telephone networks.

The purpose of the invention is to improve the noise immunity.

FIG. 1 shows a block diagram of a frame alignment receiver; in fig. 2 and 3 are time diagrams explaining his work.

The frame alignment signal receiver contains register 1, first C-flip-flop 2, decoder 3, drive 4, second 5 and third 6 0-flip-flops, AND 7, block 8, clock frequency selection, delay element 9, generator equipment 10, channel distributor eleven.

The receiver group synchronization signal works as follows.

The group signal containing undistorted clock signals of the software type (Fig. 2e) is fed from the communication line to the input of the receiver group signal. The clock frequency extraction unit 8 extracts from it a clock frequency (Fig. 2a), input to the gate of the decoder 3, and a delay element 9, from the first output of which the double clock frequency (Fig. 2d) is fed to the clock input of the generator equipment 10. Clock frequency (Fig. 2c) from the second output of the delay element 9 advances through the register 1 the group signal. The clock signal recorded in register 1 forms at its outputs a certain combination of signals (Fig. 2e) arriving at the information inputs of the decoder 3. The coincidence of these signals with the corresponding clock pulses at the input of the gating leads to the formation of a "response" signal at the output of the decoder 3 ( Fig. 2g), unambiguously corresponding to an undistorted clock signal. The output signal of the decoder 3 is fed to the clock input of the second C-flip-flop 5, the installation input of which receives the clock frequency (Fig. 26) from the third output of the delay element 9, flashing and holding the second три-flip-flop 5 in the state at which its inverse output supported "single" signal. From the third clock output of the generator equipment 10, the installation input of the third C-flip-flop 6 receives a command (Fig. 2h), which is ahead of time the output signal of the decoder 3 and sets the inverse output of the third C-flip-flop 6 "unit" signal (Fig. 2k) which is fed to the information input of the second три-flip-flop 5. The input “single” signal is written to the second C-flip-flop 5 by the forward (positive) front of the output signal of the decoder 3, and the inverse output of the second C-flip-flop 5 forms “zero” the signal is stored only until the next pulse of the clock frequency from the third output of the delay element 9 arrives at the installation input of the next time delay (Fig. 26). The second C-trigger 5 is transferred to its original state, in which the “single” signal is again set at its inverse output. The rear (positive) front of the output signal of the second C-flip-flop 6 and translates the latter into the initial state, in which the “zero” signal is at its inverse output. The third C-flip-flop 6 returns to its original state because at the moment when the positive edge of the control signal arrives at the clock input, the setup input is locked with a “single” signal (Fig. 2h), and the information input is not involved in this circuit, which is equivalent to the level of the “single” signal, which is recorded in the third C-trigger 6, forming a “single” signal at the free direct output and “zero” at the inverse output.

At the same time, the first “single” symbol of the synchronization signal enters the information input of the register 1 at the information and installation inputs of the first C-trigger 2, which are connected together, and the installation input is closed. The clock input of the first C-flip-flop 2 receives a command (Fig. 2m, Fig. Za) from the second clock output of the generator equipment 10, which coincides in time with the first symbol of the clock signal, and writes the "single" signal to the first C-flip-flop 2, setting to its output is a “single” signal. The second “single” symbol of the sync signal again locks the setup input and does not change the output state of the first C-flip-flop 2. The “single” signal from the output of the first C-flip-flop 2 is fed to the information input of the drive 4, to the clock input of which a command is issued (Fig. 2l, Fig. Sv) from the first clock output of the generator equipment 10, coinciding in time with the second symbol of the clock signal, and the clock signal is recorded in the drive 4. After receiving in a row the undistorted clock signals in the amount determined by the capacity of the drive 4 at the input synchronism, the accumulator 4 is filled and on its first output a “zero” signal is set (FIG. 3), the I 7 element locking on the first input, and the “single” signal (FIG. 2C of FIG. 3) from the inverse output of the third E> non-trigger passes to the output element And 7 (Fig. Z). This situation corresponds to the synchronism mode, when the start of work (phase) of the local generating equipment 10 coincides with the start of work (phase) of the generating equipment 10 re 4

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cottages. At the second output of drive 4, a “single” signal is set (FIG. 3), which is equivalent to the absence of a blocking signal at the corresponding input of the channel distributor 11, which, as commands are received from the control outputs of the generator equipment 10, distributes the group signal coming from the receiver group signal on his information entry on information exits.

In various situations arising during the transmission of sync signals over the communication line, in the first and previous cycles, undistorted sync signals arrive at the receiver input (Fig. 3a), which leads to the establishment of the synchronism mode, which is actually determined by the "zero" state of the first output of the accumulator 4 and the element output And 7. The distortion in the second cycle of the third symbol of the clock signal (conversion of the “zero” symbol to the “single” one) does not deduce the receiver and generating equipment 10 from the synchronism mode, since the first two characters are The signals are not distorted and are perceived by the first три-trigger 2 and drive 4 in the order described above. In this case, the output state of the first S-flip-flop 2 (Fig. 36) and the outputs of drive 4 (Fig. ZH, h) is similar to the state in the first cycle and can be stored at the positions of the sync signal for as long as the distortion does not affect the first two symbols of the sync signal received for the proposed option receiver.

In the third cycle, the first character in the sync signal is distorted (the “single” character is converted to “zero”). The “zero” signal at the place of the first clock symbol arrives at the installation input of the first три-flip-flop 2, regardless of the state of the Other inputs, opens it, moving the first-flip-flop 2 to the position at which a “zero” signal is generated at its output (FIG. 33). At the command (fig. Sv) from the first clock output of the generator equipment 10, the information about a single distortion of the clock signal fits into the drive 4. At the command (Fig. 36), the third три-trigger 6 is turned on from the third clock output of the generator equipment 10 and at its inverse output a “single” signal is formed (Fig. Ze), which will be stored because there is no signal at the output of the decoder 3, for clock signal distortion. The drive 4, calculated on K consecutive errors, does not change its state and continues to maintain synchronism mode.

In the fourth cycle, there is an undistorted clock signal and commands from the clock outputs of the generator equipment 10 and

decoder 3 all blocks of the receiver are in the state corresponding to the synchronism mode.

In the fifth cycle, the second clock symbol is distorted. In this case, the first character is written to the output of the first три-flip-flop 2, but the “zero” character received after it, acting on the setup input, translates the first ϋ-flip-flop 2 into a state in which the output is a “zero” signal, and this is recorded in accumulator 4. If in K consecutive cycles any distortion of any of the first two symbols of the sync signal occurs, the accumulator calculated for K consecutive errors will fill up and a “single” signal will be generated at its first output (Fig. 3). The inverse output of the third третьего-flip-flop 6 also results in a “single” signal (FIG. 3a) due to the absence of a signal at the output of the decoder 3, caused by distortions in the sync signal. The coincidence of these "single" signals at the first and second inputs of the element And generates at its output a "single" signal, which enters the phase setting input of the generator equipment 10 and stops it until the first undistorted sync signal appears at the receiver input. On the outputs of the generator equipment 10 are missing all the commands.

The “zero” signal (FIG. 3) from the second output of drive 4 blocks the channel distributor 11, prohibiting the distribution of the group signal to the information outputs of the receiver. Communication is interrupted for the entire search for a state of synchronism. Received at the input of the receiver clock signal in a cycle (CN) forms the output of the decoder 3 command, which translates the third ϋ-trigger 6 in the "zero" state. In this case, the prohibiting command is removed from the phasing input (Fig. Over) and the generator equipment 10 switches to the clock frequency division mode. At a time interval equal to the cycle, at the clock outputs of the generator equipment 10, commands are received that arrive at the corresponding receiver units, and the like signal of the group signal is tested. If at these positions there is an undistorted clock signal, then information about this is recorded in the drive. If there is no sync signal at the test positions, the generator equipment 10 stops again and the device proceeds to test the subsequent positions of the group signal.

When a predetermined number of consecutive undistorted clock signals arrives at the receiver input, for which drive 4 is calculated for synchronization input, it is filled in and all blocks of the receiver are cyclic signals

five

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synchronization is put on hold. Channel distributor 11 opens and communication is restored.

Thus, the proposed set of blocks and links, forming a frame synchronization signal receiver of a multichannel digital transmission system with time division channels, makes it possible to search for the synchronism state for all K symbols of the multi-symbol clock signal and is not inferior to the known receiver in search time.

The proposed receiver maintains the state of synchronism with respect to a fragment (part of symbols) of a sync signal, consisting of r symbols, without reacting to the distortions of symbols outside the fragment.

Under equal conditions of signal transmission, given that the probability of distortion of one character in the communication line is equal to B, and T <K, the proposed receiver has, in synchronization mode, protection from "failures" arising in the communication line, K / g times greater than known receiver, which leads to a decrease in the same number of times unproductive communication interruptions, and ultimately to improve the quality of communication.

1_Г

Phi 2

mr

1SHL1 Cycle 2 CycleZ Cycle H Cycle5 Cycle K * 1 Cycle B + 2

ζ - _and ---- C ---- _and ---- _and ----

b —and ---- [g

Mr. ----- ca ------- 1

e

Well

s

and

synchronization search

Fi.Z

Claims (2)

CYCLIC SYNCHRONIZATION SIGNAL RECEIVER, containing a clock frequency extraction unit · and a series-connected drive and an element, the output of which is connected to the generator phase setting input, the control outputs of which are connected to the control inputs of the channel distributor, whose information input is combined with the input of the clock selection module frequency and with the information input of the register and is the input of the receiver group signal, while the outputs of the register are connected to the information the inputs of the decoder, and the outputs of the channel distributor are information outputs of the receiver, characterized in that, in order to increase the noise immunity, the first, second and third ϋ-triggers and the delay element are inputted into it, and the output of the block is connected to the input of the gating extracting the clock frequency signals, with the first, second and third clock outputs of the generator equipment connected respectively to the clock input of the drive, the clock input of the first O-trigger and the setup input of the third ϋ- the rigger, the inverse output of which is connected to the second input of the And element and the information input of the second три-flip-flop, the inverse output of which is connected to the clock input of the third г-flip-flop, while the first, second and third outputs of the delay element are connected respectively to the clock to the input of Te / Λ non-equipment, the clock input of the register and the installation input of the second три-flip-flop, to the clock input of which the sub-I keys of the decoder output, and the information- and installation inputs of the first ϋ-flip-flop are combined with the input group signal of the receiver, and the output of the first три-flip-flop is connected to the information input of the drive. 1177932 2 one 1177932