SU1046959A1 - Device for coding and decoding signals in digital-data transmission systems - Google Patents

Abstract

A DEVICE FOR CODI $ DATING AND DECODING SIGNALS IN DIGITAL DATA TRANSMISSION SYSTEMS, containing on the transmitting side a chronizer and an encoder, and on the receiving side a pulse shaper, a clock pulse generator and a decoder, which also has a gain, and a decoder, which also has a gain, and a decoder, which has a gain, and a decoder, which, in the same way, has a pulse, a pulse shaper, a pulse shaper, and a decoder that, in a way, has a gain, and a decoder, which, in a way, has a pulse, a pulse clock, and a decoder that, in the transmitting side The connected input register and the parcel matching unit, the output of which is connected to the input of the encoder, made in the form of serially connected prohibition block, block. delay and pulse generator, to the second input of which and the first input of the output analysis block the second output of the inhibit block is connected, the first input of which is the encoder input, and the output of the output analysis block is connected to the second input of the inhibit block, the second output is connected to the second input the prohibition unit, the input of the input gate being the input of the device, and on the receiving side a block for determining the temporal position of the pulses is input, to the input of which the output of the pulse former is connected, and output of the unit for determining the temporal position of the pulsed signal (To the decoder input, made in the form of serially connected delay unit, analyzer for the structural features of signals and output unit, to the second input of which the output of the pulse generator is connected, to the O input of which the second output is connected 42 X of the analyzer of the structural features of the signals, while the input of the delay block in: O is input from the decoder. i "; about

Description

I10 The invention relates to.  communication and transmission technology and can be used in digital communication systems, telemetry, television and phototelegraphy, as well as in digital pa- raction storage equipment.  A device for transmitting digital signals is known, which contains a memory element and a comparison circuit at the receiving side of Cl.  However, the known device does not have low reliability.  The closest technical solution to the present invention is a device for encoding and decoding signals in systems, digital data transmission, comprising a chronizer and an encoder on the transmitting side, and a pulse driver, a clock generator and a decoder 2j on the receiving side.  However, the known device has low reliability.  The purpose of the invention is to increase credibility.  To this end, a device for encoding and decoding signals in digital data transmission systems, which contains a chronizer and an encoder on the transmitting side, and a pulse shaper, a clock pulse generator and a decoder on the receiving side, and a serially connected input register and a parity comparison unit, entered on the transmitting side. connected to the input of the encoder, implemented in the form of sequentially connected block of the prohibition, delay block and pulse generator, to the second input of which and the first input of the block The output of the sipnals is connected to the second output of the inhibit block, the first input of which is the input of the encoder, and the output of the output analysis block is connected to the second input of the inhibit block, and the input of the input register is the input of the second input block , and on the near side, a block of a certain temporal position of pulses is inserted, to the input of which the output of the pulse former is connected, and the output of the pulse temporal position impregnator of the pulses under the input of the decoder , implemented as a series-connected delay unit. anapiser structurally. signals and a data output unit, to 59 the second input of which is connected to the output of the pulse burst generator, to the input of which is connected the second output of the analyzer of structural features of signals, while the input of the delay unit is the input of the decoder.  FIG.  1 shows a structural electrical diagram of the device side for encoding and decoding signals in digital data transmission systems; in fig.  2 - the same, the receiving part; in fig.  3 - functional block diagram cpv. check parcels; in fig.  4 blocking scheme; in fig.  5 is a diagram of the delay unit in fig.  6 is a block diagram of the analysis of output signals; in fig.  7 is a block diagram for determining the temporal position of pulses; in fig.  8 is a diagram of the delay unit in fig.  9 . - diagram of the analyzer of structural features of signals; in fig.  10 - the first functional diagram of the shaper clock signal generator; FIG. 11 is a block diagram of a symbol synchronization block; in fig.  12 . - block diagram of group synchronization; in fig.  13 second variant of the block diagram of the clock detector; in fig.  Fig. 14 - timing diagrams, explaining n (: the processes of encoding signals; Fig.  15 shows timing charts explaining signal decoding processes.  I / A device for encoding and decoding signals in digital data systems contains on the transmitting side an input register 1, a parcel comparison unit 2, a code (p 3, containing a prohibition block 4, a delay block 5, a pulse shaper 6, an output signal analysis block 7, a chroniser 8, on the receiving side, a pulse driver 9, a temporal position determination unit 10, a decoder 11 containing a delay unit 12, analysis 1, 13 structural signs JOB, an information output unit 14, a burst generator 15, a TfliKTOBbix pulse generator 16; The package contains elements, and 17, the memory element 18; in addition, in the encoder 3, the prohibition block 4 contains the prohibition elements 19, the delay block 5 contains delay elements 20, the output signal output block 7 contains the OR element 21, the elements 22 and 23 delays, an additional element OR 24; the temporary position determining unit 10 contains AND 25 elements; in decoder 11, block 12 posteriorly contains delay elements 26; the structural feature analyzer 13 contains OR element 27, delay elements 28, elements OR 29, triggers 30, delay element 31, counter 32; shaper 16 clock pulses (the first option) contains a block of 33 symbol synchronization, block 34 group syncronization. block 35; forming a sequence of output pulses; the symbol synchronization unit 33 comprises a differentiation circuit 36, a single vibrator 37, a discriminator 38, a filter 39, a tracking generator 4O, a block 41 for generating output pulses; the group synchronization unit 34 contains a sync pattern identifier 42 consisting of a shift register 43, a decoder 44, an analyzer 45, a divider 46, a decisive block 47, a phasing unit 48, an additional analyzer 49, an out of sync detection unit 5O, a trigger 51, a divider distributor 52; the clock pulse generator 16 (the second option) contains a sync signal extraction unit 53. fishing, controlled oscillator 54, discriminator 55, control element 56, output pulse shaping unit 57, A device for encoding and decoding signals in digital data transmission systems works as follows.  The input of the second register 1 of the transmitting side is received by a sequence of binary signals of duration (FIG.  14 ).  The values of the next three characters of the input sequence arrive in block 2 of the parcel comparison, where they are compared with the program values of the symbols 111, 1O1, O1O, 000, specified in the registers of the memory element 18.  If the current values of the characters in the input sequence coincide with one of the software combinations, single signals of duration are formed at the output of the And 17 elements (Fig.  14b).  These signals are separated by separate circuits to the corresponding information inputs of the prohibition elements 19 of the prohibition block 4, the control inputs of which receive control signals with a length of 2To from the output of the block 7 analysis of each code signals (Fig.  14-6).  Such signals are formed from the output signals of the prohibition block 4 by extending them in duration to 2 Ty with the help of the elements OR 21, the elements 22 and 23 of the delay to TO and the additional element OR 24.  The generated control signals exclude the passage through the prohibition elements 19 of the block 4 of the prohibition of any signals in the ST interval, if in block 2 of the parcel comparison the current characters are matched with one of the software combinations.  This is equivalent to the transition to the analysis of the next three characters of the input sequence of binary signals that are separated from the current by the ST interval.  If such a match is not fixed, a transition is made to the analysis of the next three characters of the input sequence, which are separated from the current ones by an interval.  The output signals of the prohibition unit 4 on the corresponding circuits are sent to the driver of the pulse generator 6 directly or are preliminarily delayed in the delay unit 5 (Fig.  14).  Thus, if in block 2 of the parcel comparison a combination of symbols 111 is fixed, the output signals of the prohibition block 4 are fed to the input of the driver 6 pulses without delay.  For the input combination of 1O1 symbols, in block 5 of the delay, a delay of 0.257 ,, was set for the first delay element 20, a delay of 0.501: 0 was established for the combination of symbols 010 for the second delay element 20, and - holding 0.75.  The pulse shaper 6 generates a sequence (of binary signals signals, the minimum pulse duration of which is equal to tTo (FIG.  146), and the fronts (bit transitions) of the parcels are fixed relative to the ciscrete time points of the input signals with a duration with a delay of 0, 0.25, 0,, 0.75 o, depending on the structure of the input signals (111, 101, 010, 000) .  The remaining code combinations (1000, 001, BUT, 011) are not encoded during the transmission, but are unequivocally restored upon reception.  Synchronization of the delay unit 5 and, the output analysis unit 7 is performed by the signals of the chroniser 8.  Restore the original sequence.  The binary network signals are received by the same sequence with the help of a semiconductor device, since the temporal position of the parcels on the T7 interval is rigidly fixed relative to the coded combinations of 111, 1O1, 010, LLC symbols with the delay being equal to O; 0.25 0.50 T ,, and 0.75TO.  The decoding device works as follows.  The input pulse generator 9 receives a sequence of input signals (FIG.  15a), from the output of which the signals are simultaneously applied to the information {data inputs of the elements AND 25 of block 10 for determining the temporal position of the pulses.  To the control inputs of Commodity I 25 from the imager, 16 clock pulses are separated from each other with relative update O; O, O, 5O TG, and -0.75T, a sequence of control pulses is applied.  The temporary position of the input pulses is determined by the moments of transition (from the zero (single) level to the single (zero) level) (Fig.  15b) and corresponds to a specific structure of the original sequence of encoded characters 111, O1, 01O, LLC.  The signals from the output of the unit 10 for determining the temporal position of the pulses are outputted in separate circuits depending on the point in time at which the input sitel coincides with the control pulses.  So (FIG.  156), if the input signals were received without delay (t) relative to the beginning of the initial pulses, which follow from the frequencies io l / lTc,, then the output pulses from the first output of the pulsing position determining unit 1 are fed to the first input of the delay unit 12, where it is delayed by the first delay element 26 at the time of 1H.  Input: Delayed signals, 252 /. are output from the second output of block 10 for determining the temporal position of the pulses and are fed to the second input of block 10, where with the help of the second delay element 26 are delayed by the time O, 75TH. ; pulses and go to the third input of the delay unit 12, where with the help of the third delay element 26 are delayed by the time of 0.50Tr.  The input signals received with a latch ,, are output from the fourth output of the pulse detection unit 10 and arrive at the fourth input of the delay block 12, where they are delayed by time 0, using the fourth delaying element 26.  Thus, the unit 10 for determining the temporal position of the pulses plays the role of a time selector.  Pulses from the output of block 12 of the delay on separate circuits arrive at the element OR 27 and the delay elements 28 at the time: the analyzer 13 structural features.  The delay T is necessary for normal operation of the device.  The pulses from the outputs of the elements of the latching 28 are applied to the elements OR 29, and the triggers 30 V of the unit state (111) are set.  The pulses from the second delay element 28 through the initial, fourth, and fifth elements OR 29 set the triggers 30 to the single, zero, and single state (1O1), respectively.  The pulses from the third delay element 28 through the second, third and sixth elements OR 29 set the triggers 30 to the zero, one and zero (O1O) states, respectively.  The impulses from the Bykod of the fourth delay element 28 through the second, fourth and sixth elements OR 29 set all the triggers 30 to zero (JV).  Impulses with  the trigger 30 is fed to the input of the block 14 information output.  The impulses from the OR 2 7 element serve for the pulse burst generator 15 as a signal for reading information from the counter 32 and issuing the pulse burst of the element 27 to information output unit 14.  Pulses through the delay element 31 on Tz2. , which ensures the normal operation of the device, also goes to counter 32, dropping it to zero with x; then, after which counter 32 starts counting the clock pulses again, arriving from the driver 16 clock pulses, the number of which coincides with the number of bursts in the current interval .  The values of the parcels 001, 011, 1OO, and 110 of the current interval of decoders 1i are restored according to the following rule.  If the last three parcels look like (LLC), then the two previous parcels are assigned values inverse to the value of the last parcel 710 of the cocorate interval. .  The following pair of parcels are assigned values, inverted values of the previous pair, and so on. P.  The restored signal has via sequences. . .  O01100111 (. . .  11О011ООО).  If the last three transmissions of the interval have a win 101 (O10), the premise preceding this combination is assigned the value equal to the value of the last transmission of the interval.  The next pair of parcels is assigned the values inverse to the value of the next parcel, and so on. d.  In this case, the recovery signal in the decoding interval has the form of a sequence. . . 0011001101 (. . . 1100110010) (FIG.  15g)  The direct and inverse values of the indicated parcels are stored in the registers of the memory of the generator 15 of a burst of pulses and, depending on the values marked out; in the analyzer, 13 structural features of the signals are rewritten into block 14 of the information output.  The clock recovery and matching (phasing) of the pulses by the followers of the arms are performed by the driver of 16 clock pulses.  The structure of the 16 clock pulse generator is determined by the purpose of the device for encoding and decoding and the method of transmitting the clock signals as a whole and to the system where the proposed device is an integral part.  This task can be solved in two ways. Firstly, by transmitting and subsequently restoring the original symbol frequency, relative to which a sequence of pulses can be formed, spaced from the clock points of the frequency pulses; 0.25170; 0.5T; 0.75T.  Secondly, nyTeN; restoration of the symbol frequency i х, „l with the phasing of tactile points of this often“. .  you to the clock points of the frequency to.  what is necessary for fixing the origin of a sequence of pulses having a delay Γ; 0, O, 5Go; 0,70Go.  There are several technical possibilities for transmitting and restoring the symbolic frequency i Q or t at the receiving side, depending on which the driver of the 16 clock pulses is organized to obtain at its output the required clock signals.  The transmission of clock signals can be carried out on a separate synchronization channel 59 or for this purpose a common information channel of the system is used.  In a digital information channel common system, the transmission of sync signals can be carried out in a separate time stream or in a common stream simultaneously with the transmission of information.  In this case, there are two options for transmitting and restoring a synchronic and, accordingly, two variants of the structure of the 16 clock pulse generator.  The first variant of the recovery of the sync signals is based on the allocation of the symbolic frequency f о 4 о from the received digital signals.  To temporarily assign a sequence of output pulses to the phase of the signals of frequency t in a digital system, signals of a certain structure should be periodically transmitted in specially designated time intervals, acting as group synchronization signals.  As such signals, signals of a known structure should be selected, which are strictly periodic sequences of signals of type 111. 111. . .  or a combination with socks 111, 101, 010, LLC.  The most suitable for these purposes are the original signals of ty.  pa 111. 111. . .  or a combination of these signals with digital signals of other types, the transcoding of which leads to the required pulse sequence, which contains the initial frequency loi and its phase corresponds to zero (T-0) with respect to the frequency pulses to.  This variant of the recovery of sync pulses corresponds to the time-divided signal systems known in the literature, B which for reconstructing.  Newly transmitted signals, besides symbolic synchronization, require a group t jm to synchronize, ensuring the fixing of the time of the beginning of the counting of segments of pulse sequences of a certain time interval, in this case with the tracking frequency LO the structure of the former 16 clock pulses synchronization unit and group c1-sync block 34, the signals of which control the high-speed pulse trainer to form -.  no sequence of output pulses with the required time delay.  By using the symbol synchronization block 33, the symbol synchronization pulses are generated with the frequency ip.  In the process of forming symbol synchronization pulses, the signals arriving at the inputs of the aocoai- ation, to which the 16-clock pulses are connected, and the choppy pulses corresponding to the moments of the sign change of the video signal are triggered, and the vibrator 37 of the square-wave pulses are triggered.  The resulting sequence of pulses of one character in the spectrum contains a component of the symbol frequency about 1 / 4To, which is extracted by the filter 39. The signal of this frequency is adjusted by the tracking generator 4O, from which output the sync signals f 41 output pulses and are used to synchronize the group synchronization unit 3 and the output pulse sequencer unit 35.  The group synchronization unit 34 generates group synchronization signals.  An input information signal is received at its input, in which the synchronization signal of group synchronization of the external structure is periodically transmitted.  According to the principle of operation, the group synchronization unit 34 provides for searching and extracting a concentrated periodic sync group in the input signal using the sliding search method.  The signals arriving at the input of the decoding apparatus are fed to the input of the shift register 43 of the sync pattern identifier 42, where they are sequentially shifted by symbol synchronization pulses from the output of the symbol synchronization block 33.  The descrambler 44 sync pattern identifier 4 is tuned to a sync pattern structure containing a known number of zero and single symbols.  Moreover, each zero and a single pulse in the structure of the input video signal is displayed by a certain number of symbols.  If the structure of the symbols in register 43 coincides with the structure of the symbols in the decoder, a signal arrives from the output of the 42 synchro groups on the analyzer 45.  In the analyzer 45, the signals of the identifier 42 sync programs and the cycle of the pulses coming from the divider 46 at the moments when the group sync sigal should be received are received.  The analyzer 45 has two outputs: at the first a pulse is generated in case of a synchrogram identification signal 42 and a cyclic pulse, a pulse is formed at the second output in the absence of a signal from the sync pattern identification 42 at the moment the cycle pulse arrives; determines the presence of synchronism on cycles and accordingly allows or denies control.  Lane divider 46 pulses from the output of the analyzer 45 and the formation of the output pulse group synchronization.  Thus, the group synchronization unit 34 operates in the cycle synchronization mode or in the search mode.  The presence of an additional analyzer 49, an out-of-sync detection unit and a trigger 51 improves the operation speed of the group synchronization unit 34 due to a parallel analysis of the lack of synchronism and a sliding sync group search, however, this is not a problem. ztelnym.  The group sync pulse generated in the block. Phases coincide in phase with the frequency fp and together with the frequency sync pulses provide a sequence of pulses spaced at predetermined time intervals that are used to control AND 25 elements in block 1O of determining the temporal position of the pulses and in other blocks of the decoder.  The second option is based on the transmission of clock signals at the beginning of a communication session before transferring information.  As skh. rosktypov it is advisable to use pulse sequences of a constant structure of the type 111,111, ,,. In the process of encoding and decoding of which, sequences with a pulse duration and a repetition period of ZTS are formed. With the help of this sequence, the controlled highly stable stable synchronization generator of the receiving equipment is phased during the entire communication session.  Based on the generator signals, a sequence of pulses is obtained with the required time delay for the operation of the elements AND 25 of the block 10 for determining the time position

impulses and other units of the coking equipment. It is possible that the synchronization information is transmitted both at the beginning of the communication session and during the transmission of information at specially designated time intervals. In this case, the control of the presence and maintenance of synchronism in the system is provided. The structure of the additional clock signals remains the same. In this case, the stability requirements of the clock generator of the receiving equipment can be reduced, which simplifies the synchronization path of the entire system.

In this synchronization variant, the input of the clock generator 16 is connected to the output of the communication channel parallel to the input of the pulse generator 9, and the structure of the clock generator 16 corresponds to the structure of inertial synchronization devices known in the literature.

By means of the block 53 of the synchronization signals, the sync signals are selected, which carry out the adjustment of the controlled oscillator 54 at a frequency of ± 0 with the accuracy of the ao phase. In the output pulse shaping unit 57, a sequence of output pulses is formed with a desired time delay.

In a digital system with a separate synchronization channel, the receiving part of the synchronization channel contains a serially connected receiver of sync signals and a block for forming a sequence of pulses with the required delay

The input of the driver 16 clock pulses in this case is connected to a separate input of the decoding equipment.

In this case, via the sync channel, it is advisable to transmit signals of the frequency o about which a sequence of output pulses is formed.

Considered options for transferring sync information, based on using a separate sync channel or from a mixed sync channel with transmitting sync channels at the beginning of a communication session or extracting sync signals from a common channel transmitted through a group signal, should be considered valid and legitimate, since the proposed device for encoding and decoding is part of to a digital system, which can be referred to as highly informative communication and data transmission systems, as well as digital storage equipment data that is characterized by a large variety of synchronization paths.

Thus, the device for encoding and decoding the signals ensures the minimum duration of the output digital signals to 2.25 T. This effect is achieved if four additional positions are allocated within the batch of the original sequence to accommodate the front of the bursts of the output sequence. An increase in the number of allowed temporary positions, for example, up to eight, prevents an increase in the effect achieved.

Tl

26

I

26

 by them

IT

3

.

Fig.9

33

35

FIG. ten

FIG. //

ig //

55

53

5s

S7

FIG. 13

||||| iGGP GP.P7Pl.1 /. /. l f nffff} orf fmf, t.e J7nfT7 fi. itll, l.t / П7f} ffmf fП f fftmJ t.f fШffГ fШf f, fГf7ЛfTn f

./ .. | 77 |., P77 ....

d

 .Illllllltlllllilllill tilllttlllMtltit g P i ti I I P I I t I I I I till

| PM.7

I IHIIIIIIni II 111

111 III I

D11111 and 111 I 111 1 and In n 1

I n 11 TI

I I

II

11i 11-

..7} .HP.P

11111111

  - EL

Ii.

 II I

 II 111 ii I tl I I I in n

f.f3Tf FIG. /

Claims (1)

DEVICE FOR CODING AND DECODING SIGNALS IN DIGITAL DATA TRANSFER SYSTEMS, containing on the front side the clock and encoder, and on the receiving side a pulse generator, clock generator and decoder, characterized in that, in order to increase the reliability, the input side is connected in series with the transmitting input a register and a parcel comparison unit, the output of which is connected to the input of the encoder, made in vice series-connected block prohibition, delay unit and pulse shaper, to the second input of which and the first input of the output analysis block is connected to the second output of the inhibit block, the first input of which is the input of the encoder, and the output of the output analysis block is connected to the second input of the inhibit block, the first output of the inhibit block is connected to this input ^ of the register is the input of the device, and on the receiving side, the block for determining the alternate position of the pulses is inserted, to the input of which the output of the pulse shaper is connected, and the output of the block for determining the temporary The position of the pulses is connected to the input of the decoder made in. in the form of a series-connected block · delay, an analyzer of structural signs of signals and an information output unit. generation, to the second input of which the output of the pulse train generator is connected, to the input of which the second output of the analyzer of structural signs of signals is connected, while the input of the delay unit is the input of the decoder. tut t