SU788374A1 - Analogue-digital converter with digital correction for errors - Google Patents

Description

one

The invention relates to measurement technology and can be used in an automatic measurement system, as well as an autonomous measuring device with an automatic digital correction of additive and multiplicative errors of converting an analog value to a digital code.

An analog-to-digital converter with automatic calibration is known, containing sources of measurable and two reference voltages, the outputs of which are connected via a analog switch to a 15-frequency-to-frequency converter, reversible counters, a reference frequency generator, a control device, and elements in addition, it contains memory registers, decoders, and a compare block. In an analog-to-digital converter with automatic calibration upon command of the calibration, the control device alternately connects the sources of the first and second reference voltages to the input of the voltage-frequency converter 25. This process continues until the reverse meters and memory registers are set to the exact degree specified.

This value of the zero multiplier (initial setting) and the calibration multiplier (measurement time), which, when measuring an unknown voltage, compensates for zero care errors (additive error) and slope changes (multiplicative error) of the voltage-frequency converter. In other words, after several calibration cycles by the method of successive approximation, the values of the initial setup and the measurement time are generated, at which, regardless of the change in the characteristic of the voltage converter, the codes corresponding to zero and full scale voltages (lower and upper limits) are equal to the given value degree of accuracy given by ij.

The drawback of the device is the reduced speed of the converter, due to the fact that the values of the zero offset factor and the calibration multiplier are generated after several non-operative calibration cycles, i.e. several cycles of successive approximation.

Known analog-to-digital converter with digital error correction

containing the sources of the measured and two reference voltages, the voltage-frequency converter, the input of which through analog switches is connected to the voltage sources, the control unit, the first three inputs of which are connected to analog switches, the first, second, third, fourth elements And, the first inputs of which are connected to the fourth fifth, sixth and seventh outputs of the control unit, respectively, and the second inputs of the first and second elements AND are connected to the output of the voltage-frequency converter, the first and the second reversible counters, the inputs of which are connected to the outputs of the first second, third and fourth elements And, respectively, the reference frequency generator, the first and second summing counters, the output of the second summing counter is connected to the input of the control unit whose binary multiplier inputs are connected to the outputs of the first summing and second reverse counter, and the output is connected to the input of the second summing counter, the OR element, the inputs of which are connected to the fourth and fifth outputs of the control unit, the fifth element AND the first input of which is connected to the output of the reference frequency generator, the second input is connected to the output of the OR element, and the output is connected to the input of the first summing counter, the second inputs of the third and fourth elements AND are connected to the output of the voltage-frequency converter 2.

The disadvantage is the reduced speed of the converter, due to the fact that there are 3 calibration pushes and only after that the measurement cycle follows. At the same time, the duration of the third calibration push and equal to it, the duration of the measurement cycle is comparable to the duration of the first hit of the vibration and, in particular, equal to it, if the voltage-frequency converter does not have zero care errors and a slope change. In addition, a disadvantage of the known device is the complexity of the design, for example, the control unit, the parameters of the commands of which depend on the magnitude of the voltage being measured.

The purpose of the invention is to increase the speed and accuracy of the conversion.

The goal is achieved by the fact that in an analog-digital converter with digital correction norpeuJHOtes containing the first and second sources of the reference voltage, the source of the measured voltage, which through the first, second and third analog switches are connected to the input of the voltage-frequency converter, the output of which connected to the first inputs of the first, second and third elements, And the outputs of the first and second elements I. are connected to the subtractive and summing inputs of the first counter, respectively, the outputs of the first and third And connected to the subtracting and summing inputs of the second counter, respectively, the third counter, the binary multiplier, whose inputs are connected to the outputs of the first and third counters, the generator, the fourth and fifth elements And, entered the first and second triggers, divider and shift register, and the bus the initial installation is connected to the installation inputs of the shift register divider, counters and flip-flops, and the shift register outputs are connected to the second inputs of analog switches and to the second inputs of the first, second and The other elements are And, and the input is with the output of the divider, the input connected to the generator output and the first input of the fourth And element, the second input of which is connected to the output of the first trigger, and the output is connected to the input of the third counter, the output of the second counter is connected to the single input of the second trigger, the output of which is connected to the first input of the fifth element And, the second input of which is connected to the output of the third element And, while the single input of the first trigger is connected to the output of the fifth element And, and the zero input to the output of the binary multiplier .

The drawing shows a block diagram of an analog-digital converter containing the source 1 of the first reference voltage UQ, the source 2 of the second reference voltage and, analog keys 4,5 and 6, voltage-frequency converter 7, shift register 8, divider 9, the first, second and third counters 10, 11 and 12, the generator 13, the elements And 14, 15, 16, 17 and 18 binary multiplier 19, triggers 20 and 21, the bus initial installation 22.

The source 1 of the first reference voltage OQ is intended to set a constant voltage, the value of which does not exceed the lower limit of the range of measured voltages. For example, if the measured voltages Uj are in the range from 0 to 1 V, then the voltage Uo Od. The source 2 of the second reference voltage and f is designed to set a constant voltage, the value of which is not lower than the upper limit of the range of measured voltages. For example, if the measured voltages Uj are in the range of O to 1 V inclusive, then the magnitude of the voltage UfT, .lB. Source 3 of the measured voltage DX sets the constant voltage, the value of which is required to be represented in the digital vice. The analog switches 4,5,6 are intended for alternately connecting sources 1,2 and 3 to the input of the voltage-frequency converter 7. The voltage-frequency converter 7 is used to convert the input voltage to the frequency, and the converter has an additive error (care zero), that and multiplicative error (change in steepness of the characteristic). The shift register 8 is designed to control the analog keys 4,5,6. Register 8 has 3 bits, which are connected to control inputs of analog switches and to inputs of elements 14, 15, 16. Divider 9 is a counter to a constant capacitance, the output of which is associated with a clock (shift) input of register 8 Counter 10 binary reversible counter. The counter 11 is a counter of the measurement result of the voltage U. Counter 12 is a reversible counter. The generator 13 is designed to obtain a stable (constant) frequency. It can be made on the basis of a quartz generator. For normal operation of the device, it is sufficient that the frequency of the generator 13 corresponds to the ratio of the rp. Max., ({Const. - frequency of the generator - the maximum frequency that the voltage converter frequency can form at its output 7. Ratio (1) is shown below after considering operation of the device. Binary multiplier 19 is designed to form the number of pulses. corresponding to the ratio where Md is the number of pulses on the course of the binary multiplier number in the counter 10, the number in the counter 11, the capacity of each of the counters 10 and 11. An example of a binary multiplier is the K155IE8 microcircuit, one box of which allows you to connect a counter to 6 bits, i.e., two consequently connected K155IE8 enclosures - 12 bits, i.e. Device works as follows. At the Initial Setup command, the initial setup 22 arriving at the bus, divider 9 and counters 10, 11 and 12 are zeroed, triggers 20, and 21 are set to O state, for the first time the shift key register 8 is written 1, in the second and third bits of the register is written O. This moment is the moment n Chal operation. The single signal from the output of the first bit of register B is the closing resolution of switch 4 and the permission to pass the signal on the first input of element 14. The source 1 of the first reference voltage is connected to the input of the converter voltage-frequency 7, and the output from this the converter enters through the element I 14 to the subtractive inputs of counters 10 and 12. This process continues until the overflow pulse from the output of the divider 9 arrives at the clock (shift) input of the register 8. Duration of the first and This dimension is defined by the expression: const. Е - divider capacity; F - oscillator frequency 13. For. The proposed device values of E and F are constant. for the time Tv, counters 10 and 12 will be recorded in T H Ki, g, Nj F,. T to the number in the counter 10 (and the counter 12); the output frequency of the converter 7, corresponding to the reference voltage UQ. The moment of shift 1 from the first bit of register 8 to the second bit of this register is the beginning of the second measurement cycle. A single signal from the output of the second bit of register 8 gives permission for the closure of key 5 and permission for the signal to pass through the first input of the And 15 element. The second reference voltage is connected to the input of the converter 7, and the source 1 is turned off, since in the first discharge of the register 8 remains O. The frequency from the output of the converter 7 through the element 15 goes to the summing input of the counter 10. -This the process continues until the second overflow pulse from the output of the divider .9, which i.e. during the interval Con5t, where TU, is the duration of the second measurement interval. During the time T.o in the counter 10 for writing the number Nl F 1 1 I2; where N, j - the number recorded in the counter 10 on the summing input; Gl is the frequency at the output of converter 7, which corresponds to the reference voltage U. The number N2 will be greater than the number N,;, since the frequency Fo F.J is all that Uf Ug. Thus, after the end of the second interval liSj.sepeHHf in the counter 10, the psito (N2-N.j) O (6-) will be filled with the moment of shift 1 from the second bit into the third one is the beginning of the third measure T ,.- ,. A single signal from the output of the third bit of register 8 gives permission to lock the key b and permission to pass the signal to the first input of element 16. The source of the measured voltage DX is connected to the input of converter 7, and the source turns off, because in the second p, : i3р de register 8 remains O, Frequency of output of converter 7 through element 16 and enters element 18 and summing the input of counter 12. This process continues until the third pulse arrives at the clock input of register 8, overflow from the output Ithel 9, i.e. during the interval where the duration of the third measurement interval. During the time T., Nj will come from the output of converter 7. pulses where N; - the number of pulses from the output of the converter 7; F is the frequency at the output of converter 7, corresponding to the measured voltage U. Note that N /, as R.-PZ is Pj, in view of the fact that U (j.iLl (, -f Ugp Pulses N) c come The sum / 1 operative input of the counter 12 and the element I 18. However, the trigger 20 is in the zero state, the samgli prohibits the passage of pulses Njr through the element AND 18. As soon as the summing input of the counter 12 receives a number / Q (o 12 will be in O, a zero pulse from the output of the counter 12 is set to 1 flip-flop 20. This permits the passage of NX pulses through the el ment and 18. Note that at the output of trigger 20, the signal 1 will remain until the end of the device operation, i.e., the zero pulse from the output of counter 12 can only set this trigger to 1, and if during operation the input of counter 20 still arrives one or several null pulses from the output of counter 12, then this state of trigger 20 cannot be changed (state acknowledgment). Pulse Well, by the number NXJ N + 1, goes through the element 18 to the trigger input 21, sets trigger 21 to state 1, the permission is given for the passage of pulses from The generator 13 through the element And 17 at the input of the counter 11. This, in turn, will cause the appearance of a pulse at the output of the binary multiplier 19, which will set the trigger 21 at O. This prohibits the passage of pulses through the element And 17 at the input of the counter 11. Impulse from the output of the converter 7 under the number N + 2, the trigger 21 is set to 1 again, the enable signal to the element 17 is given, the counter 11 is filled pulse from the output of the generator 13, a pulse appears at the output of the binary multiplier 19, etc. This will continue until the pulse number N-jt; where N; is defined by the expression (7). Taking into account (8) the number of pulses from the output of the binary multiplier 19 is equal to: Ns N, NXI. - NO where N J is the number of pulses from the output of the binary multiplier for T The number of pulses at the output of the binary multiplier is related to the number of pulses at the output of relation (2). Taking into account (4) and (5), i} can be written. 1 wi Using (2), () and (7), we get Y (L ilIlllH ± g-1g; -1g ,, / Chr2-p, 1t ,, From here we can characterize the voltage-frequency converter 7 as you where FJ is the output frequency of the converter; converter input voltage / initial value of the converter frequency; k is the coefficient characterizing the converter characteristic slope. Since the measurement time is insignificant compared to the time constant of the converter parameters, k const and Fg const for this measurement. Then from (11) it follows FF (7 + F FO +

Substituting these values into

10), him

U.-Uo

those. In the counter 10, at the moment of the end of the third measurement cycle, a number is recorded that is directly proportional to the voltage being measured.

The frequency of the generator 13 must be such that when the frequency 11 is filled with the counter 11, the binary multiplier 19 would have time to form one pulse between every two pulses from the output of the converter 7, i.e. so that the inputs of the trigger 21 pulses received alternately. In the binary multiplier 19 scheme, the higher bits of counter 10 are associated with the lower bits of counter 11 (and vice versa), i.e. the last digit of the counter 10 is associated with the first digit of the counter 11, the penultimate digit of the counter 10 is associated with the second digit of the counter 11, and so on. Thus, if after the second measurement interval in the counter 10 such number is recorded as in the last discharge of this counter 1, then at receipt of every two pulses at the input of the counter 11 from the output of the binary multiplier 19, one pulse is actually generated : the row of the counter is 10 to 1, and the low-order trigger of the counter 11 changes its state twice, i.e. it will pass through the state 1). If there is a number in counter 10 such that 1 is in the last discharge of this counter, but there is 1 in the penultimate discharge, then, similarly to that described for every four pulses at the input of counter 11, at least one pulse will be generated at the output of the binary multiplier 19 ( since the trigger of the second bit of the counter 11 will necessarily change its state twice, i.e. it will go through the state 1).

In addition, when using a device in measurement information systems with processing (for example, with averaging) information, the docking of the device with computing units is simplified, since the measurement time is a constant value for the proposed device. The known devices require the use of matching blocks, so

noviv as MOMSfiT information acquisition is determined by the measured voltage.

Claims (2)

1. US patent No. 3633202, CL.340-347, 04.02.72. 2. USSR author's certificate in application number 2610467/21, cl. H 03 K 13/20.