SU660246A1 - Multichannel integrating analogue-digital converter - Google Patents

Description

one

The invention relates to the field of information technology and can be used to convert analog signals into digital codes.

A multichannel integrating analog-to-digital converter is known, comprising keys, a converter, a control and switching unit, and a counter.

This converter has insufficient conversion accuracy.

A multichannel integrating analog-to-digital converter is known, containing 7 C-chains connected to keys, the control inputs of which are connected to an address selector unit, a control unit having its own control input and connected to a counter having outputs for reading conversion results, and with the block of address selection channels, which has an output, channel numbers, 2.

The known converter has low accuracy, since it uses only analog integration, which does not provide long-term storage of the conversion results, and has non-linearity due to the finite time constant of integrators at C-chains.

The aim of the invention is to innovate

the accuracy and speed of the transformation, as well as the reduction of nonlinearity due to its correction. The goal is achieved by the fact that

into a multichannel integrating analog-to-digital converter containing a source of reference voltage, T C-chains connected to channel keys, the control inputs of which are connected to

an address selection unit connected to the control unit connected to the counter, a comparison element, an additional key, a reversible pulse counter and a memory device are entered,

the comparison element and the additional key are connected to the combined outputs of the channel keys, the reference voltage source is connected to another input of the comparison element, and the output is connected to a reversible pulse counter, a control unit and the first control input of the additional key, the second control input of which is connected to the control unit The control unit is connected to the inputs.

receiving and exiting the issuance of codes for a reversible pulse counter connected to the inputs for receiving and exiting issuing codes from a memory device that is connected to the block of address selection of channels.

FIG. 1 shows a diagram of a multichannel integrating analog-to-digital converter; in fig. 2 - timing diagrams of the operation of the converter for three channels.

Each channel of a multichannel integrating analog-to-digital converter consists of a series-connected resistor 1 (Fig. 1), a capacitor 2 and a channel switch 3. The output of each channel is connected to the first input of the comparison element 4 and to the additional switch 5, the second input of the comparison element 4 is connected to the source of the reference voltage 6, and the output with the control input of the key 5, the control unit 7 and the reversible pulse counter 8, which is connected to the output circuit and the code with the storage device 9, as well as to the control unit and 7. In turn, the control unit 7 is connected to the key 5, to the counter 10, to the block of the address selection of the channels 11, having an output on the terminal 12 of the channel number. The control unit 7 has its control input, terminal 13, and the counter 10, output terminals 14, for reading out the conversion results. The channel address selection unit is also connected to the control inputs of the keys 3 and to the memory device 9.

Multichannel integrating analog-to-digital converter operates in two cycles.

In the first cycle, multichannel simultaneous integration of the input tested voltages is performed.

The integration of input signals (Fig. 2, a, b, c), containing a periodic one and a satellite, takes place within a time 2 times the interference period. For this purpose, during this time interval, the input voltages are converted to frequencies at the output of the element of comparison 4, which are measured by a reversible counter 8 imulses and stored in memory 9.

Each channel in the storage device 9 corresponds to a certain cell, the contents of which are read and written to the reversing counter 8 synchronously with the supply of the control signal from the address selector 11 to the key 3 of the corresponding channel.

The conversion of input signals into frequencies is carried out as follows.

The input signals a, b, c are continuously integrated with the / C-chains.

The channel address selection block produces signals d, e, g, h alternately opening the corresponding keys 3 of each channel, connecting the output of the corresponding C circuit to the input of the reference element 4. Comparison element 4 compares the reference voltage from the output of the reference voltage source 6 (i / on) with the input voltage of the connected ./ C-chain (URC). The voltage on the .C-chains of the first, second, and n-channels is shown in diagrams, and, K. When 4 T of the first channel is connected to the comparison element synchronously, the contents of the first memory cell 9 are rewritten into the reversible counter 8.

, then the operation of the comparison element 4 is performed, and at its output (Fig. 2, l) an emulsion is formed that enters the reversible counter 8, as well as the control input of the key 5, which

this closes and ensures the discharge to zero of the capacitor 2 in this channel. If, then, the reference element 4 does not emit a pulse, the key 5 remains open, and the code in the reversing counter

8 - unchanged. After the comparison of the voltage from the output of the 5-chain of the first channel with the reference voltage is completed, the code from the reversing counter 8 is copied into the first cell of the memory

device 9. Then the block of address selection of channels generates a signal e, which opens the key 3 of the second channel, and at the same time connects to output element 4 the output C of the second channel. At the same time, the contents of the second cell of the memory device 9 are copied to the reversible counter 8. When the condition is fulfilled, the emulsion n is produced at the output of the element of comparison 4, the incoming

a reversible counter 8 and a closing key 5. When the condition is met, a pulse at the output of the element of comparison 4 is not produced. At the end of the comparison, the code from the reversible counter 8 is rewritten into the second cell of the memory 9.

The operation of the device when connected to the reference element 4 voltages of the lth RC circuit is similar, and

The conditions at the output of the element of comparison 4 are generated by the pulse O. After the end of the connection of the C-chain of the last channel, the element of the first channel is again connected to the element of Comparison 4:

channel, etc.

In order to eliminate the inconsistency associated with the transfer of charge from one integrating element to another when their outputs are cyclically connected to the comparison element 4, which accumulates on the input capacitance of the comparison element 4 and is proportional to the voltage difference between the outputs of the integrating elements and the number of switching cycles of the switch,

between the connections of two adjacent channels to the element of comparison 4, an additional time interval is introduced, in which all the keys 3 are open and the key 5 under the influence of a signal from the control unit 7

closes and provides a discharge of the output capacitance of the keys 3 and the input capacitance of the element of comparison 4.

In the first cycle of operation of the multichannel integrating analog-digital converter, the reversible counter 8 operates in the summation mode, the key 3 in this operation cycle does not connect the reference voltage f / oT to the input of the comparison element 4.

After a time multiple of the interference period has expired, the control unit 7 outputs a signal to the block of address selection channels AND, which closes all the keys 3, except for the key connecting to the comparison element 4 U C-chain integrating the reference voltage Usf, the second cycle starts operation of the converter, during which the multichannel simultaneous integration of the reference voltage Uat is performedThe conversion of the reference voltage into a frequency in the second cycle is performed similarly to the conversion into the frequency of the input voltages the first measure. When the condition is fulfilled, the element of comparison 4 is triggered, the signal from its output closes the key 5 and simultaneously enters the control unit 7, which produces a series of pulses entering the reversible counter 8, the number of which is equal to the number of channels in the converter. The up / down counter 8 in the second cycle operates in subtraction mode. Before the first impulse from the series coming from the control unit 7 arrives at its input, a command from the address selector 11 selects the number from the first channel of the memory 9 to the reversing counter 8. After subtracting one pulse, the number from the reversing counter 8 is written to the first cell of the memory device 9, and instead of it, the number from the second cell of the memory device 9 is written into the reversible counter 8. The second pulse from the series coming from the control unit 7 reduces the recorded reversing the counter number per unit 8, the result of the subtraction is written into the cell of the second channel memory device, and so on. d.

After the arrival of the last pulse from the series coming from the control unit 7, all the numbers recorded in the memory device are reduced by one. After the next operation of the element 4, the control unit 7 produces the next series of pulses at the input of the reversible counter 8. Counter 10 calculates the filling pulses of the time interval for integrating the voltage t / h. If, when the pulses are subtracted, the contents of the reversible counter 8 become equal to zero, then a signal is given to terminate the conversion on the corresponding channel, while the result of the conversion is read from outputs 14 and the number of the channel in which conversion is performed from terminal 12.

Improving the accuracy of the conversion is achieved by replacing the analog integration with analog-digital, while eliminating the need for long-term storage of the integration results, since the storage is performed in digital form. Indemnity compensation from

non-linearities due to the finite constant time of the integrators on the / C-chains is due to the fact that a C-chain with the same

constant time, as in channel C-chains.

Increased conversion speed is provided by simultaneous integrating on all channels, and not at different times on each channel.

Claims (2)

Invention Formula A multichannel integrating analog-to-digital converter containing a source of reference voltage, C-chains, connected to channel switches, the control inputs of which are connected to An address selection channel connected to a control unit connected to a counter, characterized in that, in order to increase accuracy and speed, a comparator, an additional key, a reversible pulse counter and a memory device, a comparison element and an additional key are connected to the combined channel key outputs, to another input The reference element is connected to a voltage source, and the output is connected to a reversible pulse counter, a control unit and the first control input of an additional key, the second control input of which is connected to the control unit, a control unit connected to the input inputs and output outputs of the reversible pulse counter codes, connected to the reception inputs and output outputs codes from a storage device that is connected to the block of address selection of channels. Sources of information taken into account in the examination 1- USSR Copyright Certificate No. 482007, cl. H 03 K 13/20, 12.07.75. 2. USSR author's certificate number 374728, cl. H 03 K 13/20, 09.09.73. figure 1 H P p p p p p {p p p t .Jl LZlZlZt ZE3ZG3xn: / t м о к м о м у- о м and ff м .i ... l .... nj JL ilJ10