SU783988A2 - Switching circular device - Google Patents

Description

The invention relates to the field of automation and computer engineering. and can be used in the construction of control systems for automated systems. 5

Known switching ring device for the main author. St. No. 705676, containing in each channel the first and second groups of AND elements and a trigger, the outputs of which are connected to the corresponding inputs of the decoder [1].

The disadvantage of this device is its low speed, due to the fact that the device polls 15 channels not only for new (current) signals, for a request, but also for signals received and already processed in previous cycles, which reduces the number of processed 20 newly received signals request per unit time.

In order to improve performance, a switching ring device containing a trigger of 25 ger in each channel is connected to the corresponding inputs of the decoder, the outputs of which are connected to the output buses, and two groups of AND elements, and the outputs of the first elements of the groups are connected to 30 single trigger inputs, the zero inputs of which are connected to the outputs of the second elements AND groups, the single trigger output of the previous channel is connected to the second inputs of the first elements AND groups of the subsequent channel, and the zero trigger output of the previous the channel is connected to the second inputs of the second elements AND groups of the subsequent channel, the zero output of the trigger of the last channel is connected to the second inputs of the first elements AND groups of the first channel and the third inputs of the first elements and second groups of all channels, and the single output of the trigger of the last channel is connected to the second inputs of the second elements And groups of the first channel and to the third inputs of the second elements And second groups of all channels, S each channel’s input, two additional triggers and two AND-NOT elements whose outputs are connected to the first inputs by AND elements of the second group, while the first inputs of AND elements are NOT connected to the zero outputs of the corresponding additional triggers, and the second inputs to the input buses and the first zero inputs of the above triggers,> the second zero inputs of which are connected to the reset bus, and the unit the inputs are connected to the corresponding output buses.

A functional diagram of a switching ring device is shown in the drawing.

The device contains triggers 1 = = 1-1 = n, the outputs of which are connected to the corresponding inputs of the decoder 2, output buses (outputs) 3 = 1-3 = 2n, elements AND 4 = 1-4 = n, 5 = 1-5 = n, constituting the first group, elements AND 6 = = 1-6 = n, 7 = 1-7 = n, constituting the second group, bus 8 clock, elements AND-NOT 9 = 1-9-0, 10 = 1-10 = 0, triggers 11 = 1-11 = 4, 12 = 1-12 = 4, input buses (inputs) 13 = 1-13 = 2p, reset bus 14.

The functioning of the switching device is as follows. Suppose that all input buses 13 = 1-13 = 24 receive processing request signals, which correspond to single logic levels, all triggers 1 = 1-1 = 4, 11 = 1-11 = 4 are in the zero state. At the same time, there are zero logic levels at the outputs of elements I'-ЕE 9 = 1-9 = 4 and 10 = 1-10 = h, and from the output buses 3 = 1-3 = 2 η there is a single logic level on only one output bus . With the arrival of a pulse on the clock bus 8 to a single state, the trigger 1 = 1 of the first channel will be translated, and a single logic level will be formed on. corresponding output bus. Similarly, with the arrival of each subsequent pulse on clock bus 8 to the single state, trigger 1 of the next channel will go over until all triggers 1, except the last, go into single states. At the same time, on all output buses 3 = 1-3 = 24, single logical levels with a duration of - will appear alternately. With a frequency equal to the period of the clock frequency, you during which input requests will be processed sequentially. When the trigger 1 = 4 of the last channel goes to a single state, with the arrival of the next pulse on the 8th clock bus, the trigger 1 = 1 of the first channel will be switched to the zero state, and a single logic level will appear on its output bus and with each subsequent clock pulse in trigger 1 of the next channel will go to the zero state, and a single logic level will 'appear sequentially on' the corresponding output buses 3 = 1-? -3 = 2 ft until all triggers 1 are set to zero. After the supply, the reset pulse on bus 14, the cycle will be repeated.

busbars 3 = 1-3 = 2) 1, the corresponding inputs of the bus 13 = 1-13 = 24 are fed skip signals (prohibition of processing) zero logic levels. Then, with the arrival of the corresponding impulse after the trigger 1 = 1 of the first channel goes into a single state, the unit logic level from the output of Element I6 »2 of the second channel will be set to the unit state and trigger 1 = 2 of the second channel and the unit logic level will be formed not on the corresponding output bus, but on the subsequent output bus, if there is no skip signal on the corresponding input bus, i.e. the corresponding output bus will be skipped.

After the processing of each requested channel is completed, the pulse from the corresponding output bus will set to a single state the corresponding of the triggers 11 = 1-11 = l, 12 = 1-12 = 4, and at the output of the corresponding element AND-NOT 9 = 1- connected to it 9 = And, 10 = 1-10 = 4, a single logic level appears, and in the next processing cycle, if there is no reset signal from bus 14, this channel will be skipped even if a request signal is still present at the corresponding input.

When removing one of the request signals, the voltage drop resulting from the input bus sets the corresponding trigger 11 = 1-11 =) 1, 12 = l-12 = h to 0, unlocking the request processing in this channel, and when a new request arrives, the same introductory bus this application will be processed in the next processing cycle. Thus, the device allows to reduce the total processing time of incoming requests.

Claims (1)

The invention relates to the field of automation and computer technology and can be used in the construction of control devices for automated systems. Known switching ring device on the main auth. St. 705676, containing in each channel the first and second groups of elements And the trigger, the outputs of which are connected to the corresponding inputs of the decoder l. A disadvantage of this device is the low speed, due to the fact that the polling device not only channels new (current) signals, request, but also signals received and processed in previous cycles, which reduces the number of processed newly received request signals in unity of time. In order to increase speed, a switching ring device containing a trigger in each channel connected to the corresponding inputs of the decoder, the outputs of which are connected to the output buses, and two groups of elements H, and the outputs of the first elements of the groups are connected to single trigger inputs, zero inputs of which are connected to the outputs of the second elements And groups, the single output of the trizgger of the previous channel is connected to the second inputs of the first elements And groups of the subsequent channel, and the zero output of the previous trigger to The input is connected to the second inputs of the second elements AND groups of the subsequent channel, the zero output of the trigger of the last channel is connected to the second inputs of the first elements AND groups of the first channel and the third inputs of the first elements And the second groups of all channels, and the single output of the trigger of the last channel is connected to the second inputs of the second channel elements And groups of the first channel and to the third inputs of the second elements AND the second groups of all channels, S each channel has two additional triggers and two NAND elements, the outputs of which are connected to the first inputs With the second group of elements, the first inputs of the I-KE elements are connected to the zero outputs of the respective additional triggers, and the second inputs are connected to the input buses and the first zero inputs of the above-mentioned triggers, the second zero inputs of which are connected to the reset bus, and the single inputs connected to the corresponding output bus. The functional diagram of the switching ring device is shown in the drawing. The device contains triggers 1 f1-1 whose inputs are connected to the corresponding entrances of the decoder 2, output buses (outputs), elements And, which constitute the first group, elements And b, constituting the second group, tire 8 clocking, elements And- NOT 9 1-9-n, triggers, n, input buses (inputs), reset bus 14, switching device operation is carried out in the following way. Let the request for processing signals to all input buses, which correspond to logical levels, all triggers, are in the zero state. At the same time, at the outputs of the elemen- tive-yo) 1 and ti, there are zero logical levels, and of the output buses η there is a unitary logical level on only one output bus. With the arrival of the pulse, the trigger of the first channel will be transferred to the single state by the clocking bus 8, and a single logical level will be formed on. corresponding to the output bus. Similarly, with the arrival of each successive impulse, by the time of 8 clocking, the trigger 1 of the next channel will go to one state, until all the triggers 1, except the last one, go to single states. In this case, on all output buses, single logical levels will appear alternately with a duration equal to the period of the clock portion, in those geniuses of which the input requests will be processed sequentially. When the trigger of the last channel transits into one state, with the arrival of the next impulse over 8 clocks, the trigger of the first channel will be transferred to the zero state, and the single logic level will turn on its output bus and with each subsequent clock pulse to zero the state will go over the trigger 1 of the next channel, and a single logic level will appear sequentially on the corresponding output buses until all the triggers 1 are set to the zero state. After feeding, the reset pulse on the bus 14, the cycle will be repeated. If during processing it is necessary to skip any channel or 1 canybv group,) corresponds to skipping output tires or groups of output 783988 tires) 1, zero logical levels are sent to the corresponding bus inputs. Then, with the arrival of a corresponding pulse after the first trigger switch triggers to one, the unit logic level from the output of the second channel element sets the trigger condition of the second channel to the unit state and the unit logic level is formed on the subsequent output bus, if the corresponding input bus, there is no signal skip, i.e. the corresponding output bus will be skipped. After the processing of each requested channel is completed, the pulse from the corresponding output bus will set the corresponding IE trigger in one state, and a single logical level will appear at the output of the corresponding NAND element connected to it, and during the next processing cycle, if there is no signal reset from bus 14, this channel will be skipped, even if the corresponding input is still present with the signal of the inquiry. When one of the signals received on the input bus is removed, the voltage drop sets an appropriate trigger to O, unlocking the processing of an e-request in this channel, and when receiving a new attack on the same input bus, this application will botana in the slezpsvdem processing cycle. Thus, the device allows to reduce the overall processing time of POSTUPPED E-polls. The invention of the switching ring device, according to ed. St. 705676, characterized in that, in order to improve speed, two additional triggers and two AND-NE elements, whose outputs are soy (ina with the first inputs of the AND elements of the second group, are introduced into each channel, the first inputs of the AND-NOT elements are connected to zero outputs correspond to | (I1ShH, additional triggers, and the second inputs to the input buses and first zero inputs of the mentioned triggers, the second zero inputs which are connected to the reset bus, and single inputs to the corresponding output 1 channels. Information sources are received e into account when ekspeotize 1. USSR Author's Certificate 705,676, Cl. H 03 K 17/02, on 02.21.77., j-t 5-g Yy | Zd ipls- felQ l "-f f3-r u u .. “n p zg / i