SU962950A1 - Device for control of interruption programs - Google Patents

Description

The invention relates to computing and can be used in multi-program computing systems.

A device is known that contains a request register, whose input is the information input of the device, a request priority decoder connected by outputs to the corresponding inputs of the request queue memory, a synchronization node and a mask register l ..

The disadvantage of this device lies in its limited functionality, as a result of which it cannot be used in computing systems operating in real time and re-. several tasks at the same time.

The closest to the one proposed by technical suas is a device containing a request register, a request priority decoder; queue storage registers for each request priority, which form the memory of request queues, synchronization node, request priority node, priority priority encoder, request priority registers, priority comparison scheme, interrupt address decoder, memory section priority registers, mask register 2} device is its complexity.

The purpose of the invention is to reduce hardware costs by comparing the newly received request with the lowest priority

10 maintenance.

The goal is achieved by the fact that a device containing a priority register, two blocks of AND elements, a memory block, a distributor of 5 pulses, an older selection node

priority, a group of blocks of elements AND, a group of output registers, a mask register and a comparison circuit, the code input of the device is connected to the information input of the priority register, the output of which is connected to the first input of the first block of AND elements, the second input of which is connected to the first output of the pulse distributor whose input is connected to the device startup input, the second output is connected to the first input of the second block of elements And, the group of inputs of which is connected to

30 by a group of information outputs of the memory block, the information input of which is connected to the first information input of the device, the second information input of which is connected to the information input of the mask register, the output of which is connected to the second input of the second block of elements AND whose output is connected to the input of the high priority selection node, the output of the first block of elements AND is connected to the input of the decoder, the group of outputs of which is connected to the group of address inputs of the memory block; the outputs of the output registers are an information group Ion outputs of the device, contains a group of decoders, a third block of AND elements, an encoder, a low priority register and a low priority selection node, the output of each output register is connected to the input of the corresponding group decoder, the output of each group decoder is connected to the corresponding AND group of inputs whose input is connected to the third output of the pulse distributor, the fourth output of which is connected to the first inputs of blocks of elements of the group, the second input of each of which Connected with the output of the high priority selection node and with the first input of the comparison circuit, the output of which is the interrupt output of the device, the output of the third block of elements I is connected to the input of the low priority selection node whose output is connected to the information input of the lower priority register whose clock input is connected to the third output of the pulse distributor, the output of the register of lower priority is connected to the input of the encoder and to the third input of each block of elements AND groups, the output of the encoder is connected to the second input comparison schemes.

FIG. 1 is a block diagram of the device; in fig. 2.- block diagram of the node choosing the highest priority; in fig. 3 is a block diagram of a comparison diagram; in fig. 4 is a block diagram of a synchronization node; in fig. 5 is a block diagram of a node for the low priority priority.

The device contains priority register 1, block And of elements 2, decoder 3, registers 4 for storing the queue for each request priority, forming memory block 5, block And of elements, pulse distributor, high priority selection node 8, comparison circuit 9, N groups of blocks 10 And elements, a group of output registers 11, a group of decoders 12, a block of 13 elements And, a node 14 for selecting a lower priority, a register 15 for a junior priority.

the encoder 16, the mask register 17, the information input 18, the second 19, the third 20 and the first 21 inputs of the device, the output 22 and the control output 23.

Node 8 select high priority consists of a group of elements 24 of the ban, the register 25 and the encoder 26 (Fig. 2). Request signals are sent to the corresponding inputs of the elements.

24 ban. The request signal of increased priority is fed directly to the corresponding input of the register 25.

The comparison diagram (Fig. 3) consists

from register 27, register 28, group of schemes 29 of coincidence, group of elements AND 30, element OR 31. Distributor 7 consists of a binary counter 32, a decoder 33 and three buses

A, B, C (Fig. 4). Selection node 14

Junior priority consists of a group of elements 24 of the ban, the same as in node 8 (Fig. 5).

The device works as follows.

By informational input 18, register 1 enters a fragment received in the memory of the message system containing the code of the priority number of this request. According to the signal from the distributor 7, through the block 2, the senders And this code is fed to the decoder 3, on one of the outputs of which a signal appears. Each output of the decoder corresponds to only one fixed priority number. Signals issued by the decoder 3 are written into registers 4 so that the number of ones contained in register 4 at any given time is exactly equal to the number of unserved requests. The signal from the distributor 7 through the block 6 elements And to the input of the node 8 receives signals from all registers 4, unmasked

the code coming from the register of 17 masks and in non-zero state. Node 8 allocates the highest priority queue and generates a priority code signal at the input of the comparison circuit 9 and for information

Claims (2)

1. USSR author's certificate in application number 2416720 / 18-24, cl. G06 F 9/46, 1976, ten 2. USSR author's certificate in application number 2420831 / 18-24, cl. G06 F 9/46, 1976 (prototype). p g 51  b Hysjjyffufff Fi. ffm node 8 f7 21 27  27. thirty X /  - 44 / 2ff tff v J Hf ( nineteen Numap Oh L . J