SU834701A1

SU834701A1 - Queue organization device

Info

Publication number: SU834701A1
Application number: SU792829675A
Authority: SU
Inventors: Аскольд Борисович Завьялов; Игорь Францевич Хомич; Владимир Семенович Медведев
Original assignee: Предприятие П/Я Г-4812
Priority date: 1979-09-06
Filing date: 1979-09-06
Publication date: 1981-05-30

Description

(54) УСТРОЙСТВО ДЛЯ ОРГАНИЗАЦИИ ОЧЕРЕДИ(54) DEVICE FOR ORGANIZING QUEUE

II

Изобретение относитс к вычислительной технике и может быть использовано в системах группового управлени .The invention relates to computing and can be used in group control systems.

Известно устройство дл организации очереди за вок, содержащее триггеры, элементы И, ИЛИ, регистр сдвига 1.A device for queuing applications is known, containing triggers, elements AND, OR, shift register 1.

Такое устройство не позвол ет организовать равноприоритетное обслуживание за вок.Such a device does not allow organizing equal priority service.

Наиболее близким к предлагаемому по технической сущности и достигаемому результату вл етс многоканальное устройство дл управлени очередностью обработки запросов, содержащее регистры, счетчики , узел сравнени , элементы И, НЕ, элемент задержки, триггеры 2.The closest to the proposed technical essence and the achieved result is a multichannel device for managing the request processing sequence, containing registers, counters, a comparison node, AND elements, NOT, a delay element, triggers 2.

Это устройство сложно из-за больщого количества оборудовани .This device is complicated due to the large amount of equipment.

Цель изобретени - повыщениё быстродействи устройства,The purpose of the invention is to increase the speed of the device,

Роставленна цель достигаетс тем, что в устройство дл организации очереди, содержащее элемент ИЛИ, два счетчика, узел сравнени , причем группа входов элемента ИЛИ вл етс группой запросных входов устройства, первый выход каждого счетчикаThe mapped target is achieved in that a device for queuing containing an OR element, two counters, a comparison node, the input group of the OR element is a group of request inputs of the device, the first output of each counter

соединен с соответствующим входом узла сравнени , введены блок пам ти, шифратор и дешифратор, адресный выход шифратора соединен с адресным входом блока пам ти , блокирующий выход шифратора соединен с первым входом первого счетчика, выход элемента ИЛИ соединен со вторым входом первого счетчика, первый выход узла сравнени соединен с третьим входом первого счетчика, второй выход узла сравнени соединен с первым входом второго счетчика,connected to the corresponding input of the comparison node, the memory block, the encoder and the decoder are entered, the address output of the encoder is connected to the address input of the memory block, the blocking output of the encoder is connected to the first input of the first counter, the output of the OR element is connected to the second input of the first counter, the first output of the node the comparison is connected to the third input of the first counter, the second output of the comparison node is connected to the first input of the second counter,

второй вход которого вл етс управл ющим входом устройства, второй выход каждого счетчика соединен с соответствующим входом блока пам ти, выход блока пам ти соединен с входом дешифратора, группа выходов дешифратора вл етс группой выходов устройства, группа входов шифратора - группой запросных входов устройства.the second input of which is the control input of the device, the second output of each counter is connected to the corresponding input of the memory unit, the output of the memory unit is connected to the input of the decoder, the output group of the decoder is the output group of the encoder, the group of request inputs of the device.

Блок-схема устройства приведена на чертеже .The block diagram of the device shown in the drawing.

Claims

The device contains the request inputs of the 1st device, the element OR 2, the encoder 3, the memory block 4, the second counter 5, the decoder 6, the comparison node 7, the outputs 8 of the device, the first counter 9. The device works as follows. The inputs 1 - m of the device are supplied with demand signals that require servicing, which, through the OR element, are recorded on the first cyclic counter 9, which determines the current queue number of the application. At the same time, with the help of the encoder 3, the application signals are converted into the corresponding Canadian n-bit binary code, and at the address corresponding to the queue number of the application, this code is written into memory block 4. In this case, if at the inputs 1 of the tamper 3 randomly several signals of the same time arrive, then the formation of the address code does not occur, and the first cyclic counter 9 is blocked. Signals for servicing the request are received at the input of the second cyclic counter 5, which records the current number served by the application from input 10. The binary channel code from memory block 4 is read at the address corresponding to the number served by the application. The address code read from block 4 of memory is converted by decipher b into a position signal — a requirement to service the corresponding channel. In the event that the second counter 5 served by the request "overtakes the first counter 9 of the priority order, the signal from the comparison node 7 blocks the second counter 5 for subsequent service signals. On the other hand, if the counter 9 "overtakes the counter 5 by an amount exceeding the memory capacity of block 4, then the signal from the comparison node 7 blocks the counter 9 for signals requiring service. The naming of the proposed device allows speeding up the processing of low priority applications. Claim device A queuing device containing an OR element, two counters, a comparison node, the input group of the OR element being a group of request inputs of the device, the first output of each counter is connected to the corresponding input of the comparison node, in order to improve speed, The device contains a memory block, an encoder and a decoder, the address output of the encoder is connected to the address input of the memory block, the blocking output of the encoder is connected to the first input of the per8 o counter, the output element OR is connected to the second input of the first counter, the first output of the comparison node is connected to the third input of the first counter, the second output of the comparison node is connected to the first input of the second counter, the second input of which is the control input of the device, the second output of each counter is connected to the corresponding input of the memory So, the output of the memory unit is connected to the input of the descrambler, the group of outputs of the decoder is a group of outputs of the device, and the group of inputs of the encoder is a group of request inputs of the device. Sources of information taken into account in the examination 1. USSR author's certificate number 425177, cl. G 06 F 9/18, 1974.

2. USSR author's certificate number 496558, cl. G 06 F 9/00, 1975 (prototype).