SU773622A1 - Multiplying device - Google Patents

Description

The invention relates to computing and can be used in the construction of specialized calculators, whose operation is based on the principles of digital information technology (i.e., associated with the number-pulse processing of information). A pervert multiplication device containing a counter, a divider, the outputs of which are connected respectively to the first and second inputsM-1 of a group of elements AND, the outputs of which are combined, as well as a controlled divider and a trigger l.

The disadvantage of this device is low speed.

The closest in technical essence to the present invention is a multiplying device containing a frequency booster, an AND element, a binary multiplier, a reversible counter, while the inputs of the first bit operand bits of the device are connected to the binary multiplier information inputs, the second operand bits. the devices are connected to the information inputs of the readout of a counter whose output is connected to the first input

element And, the second input element And is connected to the clock input of the device and the counting input of the detracting counter, the output of the element And is connected to the counting input of the binary multiplier, the inputs of the higher bits of the third operand of the device are connected to the information inputs of the reversible counter, the installation input

10 whose zero is connected to the device setup input zero, the inputs for recording the information of the reversible counter% 1, the subtracting counter and the binary multiplier are connected to the input of the device operand record 15, the outputs of the reversing counter are connected to the outputs of the higher bits of the device 2.

In this device in. each

20 cycle of computations; the multiplier multiplies the first operand X by the second operand V, represented at the clock input of the multiplier number 25 by the pulse code (CHIK .V) representing a sequence of pulses whose number is

N ,,. S4-2-,

CD

where Y and, respectively, the logical and weighting factors of the i-ro bit of the K-bit code. The duration of the calculation cycle of a known device is equal to

Tu, N ,, - t, (2)

where is the period of the following pulses at the clock input of the device.

The disadvantage of this device

is low speed.

The purpose of the invention is to increase the speed of the device.

The goal is achieved by the fact that the device for multiplying, containing / more the frequency divider, the element AND, the binary multiplier, the reversible counter, with this input of the lower digits of the first operand of the device is connected to the information

the inputs of the binary AE multiplier, the inputs of the higher bits of the second operand of the device are connected to the information inputs of the detracting counter, the output of which is connected to the first input of the AND element, the second input of the AND element and connected to the clock input of the device, the output of the AND input to the counting input of the binary the multiplier, the inputs of the higher bits of the third operand of the device are connected to the information inputs of the reversible counter, the input of which zero is connected to: the input of the installation of zero devices, inputs for recording information of a reversible counter, a subtracting counter and a binary multiplier are connected to, the recording entry of the device operands, the outputs of the reversible counter are connected to the higher bits of the device, further comprises a switch and an adder, the first information input of the switch connected to the output of the And element , the first control input is with the input of the high bit of the first operand of the device, the second control input with the input of the low bit of the second operand of the device, the second information Ion input — with the transfer output of the subtracted counter and the output of the end of the device operation; the outputs of the binary multiplier and the switch are connected respectively to the inputs of the summers of the adder, the control input of the reverse of the adder is connected to the appropriate input of the device, the information input to the young input is:

The second bit of the third operand of the device, the zero setting input g with the device zero input input, the information recording input with the recording operand input of the device, the first and second transfer outputs of the adder are connected respectively to the addition and subtraction inputs of the reversible counter, the output of the adder is connected to the lower one bit device, as well as the fact that the adder contains a counting trigger, an element and a prohibition element, an OR element, a half adder, a transfer decoder, while the inputs of the summand semi-adder are the inputs of accumulator, the transfer output of the half adder is connected to the first input of the transfer decoder, the second input of the decoder is connected to the control input of the reverse of the adder, the third, the input with output of the sum of half accumulator and pulse input of the counting trigger, the fourth input with the output of the counting trigger and the output of the sum of summator the inputs of the And and the prohibition elements are the information input of the adder, the second inputs are the input of the recording of the information of the adder, the outputs of the And and the prohibition elements are connected respectively to the S input of the counting trigger and vym input OR gate, a second input connected to the zero setting input of the adder, and the output from R-vhodomschetnogo trigger.

The drawing shows a diagram of the multiplying device.

The device contains a subtractive counter 1, the element And 2, the binary multiplier 3, the reversible counter 4, the inputs 5 of the first operand, the inputs

6th operand, clock input

7 devices, inputs 8 of the third operand of the device, input 9 for setting the device zero, input 10 for recording the operands for the device, outputs 11 for the device, switch 12, adder 13, input 14 for controlling the reverse of the device, output 15 for operation end, counting trigger 16, element 17, element prohibition 18, element OR 19, half adder 20, transfer decoder 21, result counter 22, multiplication unit 23.

The device is based on digital elements. The triggers entering the device are switched to ueifbloptae times after the end of the pulses at their clock inputs.

The operation of the device is based on the principles of digital integration (it works cyclically).

. Before the start of each cycle of operation of the device, the memory of the multiplication unit 23 and the result counter 22 contains information related to the operation of the device in the previous cycle.

Claims (2)

The CyclicBUMS begins with the arrival at the input 10 of the device, the pulse I 10, from which the 10-bit code of the third operand Z is entered from the inputs 8 into the counter 22, the 5-bit code from the inputs 6 is entered into the counter I, represented by the higher bits of the second operand code y, and the binary multiplier 3 is set to Some time after the end of E10 on the device input 7, a sequence of clock pulses (pi) is fed to the counting (subtracting) input of the counter 1 and the second input of the And 2 element on the first input of which is from the output of the counter 1 l, a control signal is given. According to the signal of counter 1, the operation of element 2 is permitted, if the contents of counter 1 is not equal to O and is forbidden, if the content of counter 1 is equal to 0. Thus, the software PI of counter 1 begins to decrease, and at the output of element 2, the sequence is generated pulses arriving at the counting input of the binary multiplier 3 and the first information input of the co1 {utator 12). The second information input of the switch 12 from the transfer output of the counter 1 receives a pulse indicating the end of the operation. The switch 12 signals the first and second information inputs, the first of which is determined by the logical value X of the most significant (the first bit of the first operand X, and the second by the logical value Vj, the younger (sixth) bit of the second operand H produces a sequence of pulses arriving at one of the inputs of the addendum addend 13. To the other input of the adjoining adder 13 from the output of binary multiplier 3, a sequence of pulses is produced, generated by a series of pulses from the output of the element And 2 and (K-1) 5-bit code x, represented by lower bits da ai K of the 6-bit code of operand X. Each pulse of the PI 12 or PI 13 sequence has a weight of 2 and is counted by counter 3. The operation mode (addition or output; output) of the counter 22 is specified with a reverse control input 14 devices so that when the signal is zero (i.e., the counter is 22 jobs & the addition, and when it is one (i.e), it is subtraction. This is done as follows. If at the inputs of the summands of the adder 13 there are signals, the n $) lusummator 20. produces a pulse of overflow, acts, with the left signal at the control input of the adder, through the decoder 21 to the summing input, and with the single input - to the subtracting input of counter 4. If there is a single signal only on one of the inputs of the addendum 13, the half adder 2 produces a pulse arriving at the pulse input of the counting trigger 16. Therefore, in the second case, the adder 13 operates as a one-bit reversible counter, pulses, re-output, the input of which is received. accordingly, the addition input or the subtraction input of counter 4. The calculation process (i.e. code generation in counter 22) will continue until the counter receives the signal from the transfer output. The transfer signal of the divider is fed to the output of the end of the operation of the device, signaling that the calculation cycle is over. Therefore, at some point after the end of this signal, the clock pulse input is stopped at input 7 of the device. On this cycle of calculations is over. Consequently, from the device outputs 11, the result of the calculation of n is the 10-bit code of the number I, whose value is determined by the expression () (М1 + М2) -2Л (3) where N1, N-2 is the number of pulses generated during the calculation cycle respectively, at the entrance to the multiply gel 3 kolvlutator 12; the logical value of the signal at the input 14 of the control reverse; code of the third operand. Moreover, N K Y Ni Vnt (xh: 5r fi-V- | w r-1 i 2) The duration of the calculation cycle i can be determined by the expression. (B) where t is the period of the following clock pulses at input 7 of the device K-1K-1 ,, ti- “KH; Гк п. f. N-2 5: H 5: H; 2 P “W-) -L ill where N is the number of pulses at the output of the element II. By comparing expressions (2) and (6), we get Tu, irT npoT / 2 (in From 1 h it follows that with identical results Calculations in the known and in the proposed device, the proposed device has a higher speed.The formula of the invention is 1. A multiplication device containing a frequency divider, the element AND, a binary multiplier, a reversible counter, and the inputs of the lower bits of the first operand of the device are connected to the information inputs. BINARY multiplier, cTapKimx inputs 1 bit of the second operand of the device is connected to the information inputs of the read counter of the counter, the output of which is connected to the first input of the element And the second input of the element And is connected to the clock input of the device and the counting input of the reading counter, the output of the element And connected to the counting input of the binary multiplier, the inputs of the bits the third operand of the device is connected to the information inputs of the reversible counter, the input of the zero setting of which is connected to the input of the zero installation of the device, the inputs of the recording of the information of the reverse with The meter, the subtracting counter and the binary multiplier are connected to the input of the one-second rand device, the outputs of the reversible counter are connected to the higher-level outputs of the device, which is different because, in order to improve speed, a switch and adder are added to it, and the first information the input of the switch is connected to the output of the element and; the first control input - with the input of the higher bit of the first operand of the device, the second control input - with the input of the lower bit of the second operand of the device, the second information input - with the transfer output of the detracting counter and the output of the device operation, the outputs of the double multiplier and switch are connected respectively to the inputs of the summers of the adder, the control input of the reverse of the adder is connected to the corresponding input of the device, the information input is connected to the input of the MS1 DDS of the third operand of the device, the input is set Novki zero - with device zero input, information record input - with device operand record input, first and second transfer outputs sum: the torus is connected respectively to the addition and subtraction inputs of a reversible counter, output., the auxiliary amount is connected to the low-end output of the device. 2. The device according to claim 1, characterized in that the adder o contains a counting trigger, an AND element, a prohibition element, an OR element, a half adder, a transfer decoder; , third 0 input - with the cyMivbJ output of the half-adder and the pulse input of the counting trigger, the fourth input - with the output of the counting trigger and the output of the sum ut: the latformer, the first entrances of the A, cops And bans. are the information input of the adder, the secondary inputs are the input of recording the information of the adder, the outputs of the elements AND and the prohibition are connected respectively to the S input of the counting trigger and the first input of the OR element, the second input of which is connected to the input of the zero setting of the adder, and the output to the R input counting trigger. Information sources, 5 taken into account in the examination  1. USSR author's certificate 404086, cl. G .06 F 7/39, 1971. 2. USSR author's certificate in application 2531456 / 18-24, 1977 (prototype).