SU762141A1 - Pulse reshaper - Google Patents

Description

The invention relates to communication technology, can be used in the regenerator pulse quasitroich code, especially in the presence of intersymbol interference.

"Known regenerator that soder- solver ⁵ INH, the threshold detector, the inputs of which are connected to the output of the amplifier with a controllable gain, an integrator whose input is connected to the output threshold detector, and an output - to the control input of the amplifier, the source of clock pulses, the output of which connected to the input of the resolver [ΐ]. ·

The disadvantage of this regenerator is low noise immunity.

Most close to the proposed pulse regenerator, which comprises an amplifier with controllable gain coeffi- cient _m, integrator, solvers, logical storage device, a source of clock pulses [2].

2

In the process of automatic gain control, the gain decreases when the pulses pass through both resolvers, or increases if the pulses pass. only through a solver with a lower threshold. This solver works optimally on the ^ -t'e. the threshold is twice less than the average level of pulses at the moments of gating. The optimal mode is preserved in the presence of intersymbol interference.

The disadvantage of the known regenerator is the reduction of noise immunity in the presence of intersymbol interference, which is associated with a deterioration in the signal-to-noise ratio.

The aim of the invention is to improve the noise immunity.

This goal is achieved by

that in a pulse regenerator containing

coefficient controlled amplifier

3

762141

the interface, the output of which is connected to the first inputs of two decision blocks, the second inputs of which are connected to the output of the clock generator, a memory block, one input of which is connected to the output of the first decision block, and the output through an integrator connected to the control input of the amplifier with controlled gain factors , an interleaved analyzer was added, an additional memory boiler block was added, shapers for reading the prohibition pulses and a third decisive „block, one input of which is connected to the second amplifier output with controllable coe ~ ₁₅ e> is the gain, and the other input is connected to the first input interlace analyzer, the first input of the second memory block and the output of the clock, and an output connected to the second inputs of the pre- storage unit 20 additionally interleaving and the analyzer, the third inputs of which are connected to the output The second decision block and the first input of the read pulse shaper, the second input of which is 25 is connected to the output of the additional memory block, and the output is connected to the second input of the memory block, the fourth input and the second output are The memory module is connected to the output and the first input of the inhibitor pulse generator, the second input of which is connected to the output of the interlace analyzer.

FIG. 1 is a block diagram of a pulse regenerator; in fig. 2 shows timing diagrams explaining its operation (in Fig. 2a, a quasi-trivial signal is shown at the output of a controlled amplifier; Fig. 26 is a signal at the output of a regenerator).

The pulse generator contains an amplifier 1 with a controlled division factor, an integrator 2, two decision blocks 3, 4, a generator of 5 clock pulses, a memory block 6, an alternator analyzer 7, an additional memory block 8, shapers 9, 10 read pulses and inhibit pulses, respectively, the third decision block 11.

The pulse generator works as follows.

The signal at the output of the memory unit takes the value "1" or "O 'in accordance with the level of the pulse at the inputs of the decision blocks 3, 4 at the clock points in time (Fig. 2, the moments O, 1, 2 ...). For a change in the output signal block

6 it is necessary that the output of the decision block 3 passes “1 *” and also the presence of “1” at the output of the decision block 11 in the previous clock interval ··. For this reason, the threshold level 112 corresponds to the level “1”.

In this case, intersymbol interference in regenerators leads to a decrease in the level of the subsequent “1”, i.e. obviously

In the presence of aerial noise, such a change in the algorithm is the reason for reducing the probability of transformation '1' to "O", which increases the noise immunity and the probability of transformation "O" to '.1' (Fig. 2, intervals 2-3, 5-6), which reduces noise immunity. In this case, information is used on the violation of the alternation of the polarity of the pulses of a quasitroich code. Upon receipt from the analyzer's output, the alternation 7 of the signal about interruption in the Ith cycle, and if there is a "1" in (U -1) -th cycle (this "1" is stored in the information memory of block 8), the imaging unit 10 generates a prohibition pulse. Impulse ban "1". mistakenly taken in the n-th cycle, "deleted" from the information memory of block 8, i.e. ke passes to the output of the generator. Such "false". units, the probability of occurrence of which could be relatively large, are shown by a dotted line in FIG. 26

It should be noted that the use of the NDV code, in which the interlacing violations are incorporated in the algorithm, does not interfere with the normal operation of the regenerator. If it is necessary to perform an inverse transformation in the regenerator (of the NOV code to another code), the analyzer 7 and the block 8 can be used for this purpose simultaneously with their execution of the functions described above.

The positive effect of the use of the regenerator is to increase the noise immunity in the presence of intersymbol interference.

Claims (1)

Claim A pulse regenerator containing an amplifier with a controlled gain, the output of which is connected to the first inputs of two decision blocks, the second inputs of which are connected to the output of a clock generator, a memory unit, one input of which is connected to the output of the first decision 762141 five unit, and the output through the integrator is connected to the control input of the amplifier with a controlled gain, which is based on the fact that, in order to improve the noise immunity, an alternation analyzer, an additional memory block, read pulse and prohibition pulse drivers and the third decisive a unit, one input of which is connected to the second output of the amplifier with controlled gain, the second input is connected to the first input of the interlace analyzer, the first input of the second memory block and the generator output clock x pulses, and the output is connected to the second inputs of the additional memory block and the interleaver analyzer, the third inputs (which are connected to the output of the second 6 the decision block and the first input of the read pulse shaper, the second input of which is connected. And the output of the additional memory block, and the output is connected to the second input of the memory block, with the fourth input and the second output of the additional memory block connected respectively to the output and the first input of the inhibitor pulse shaper, <0 whose second input is connected to the output of the interlace analyzer. about