SU758260A1 - Rapid-access storage checking device - Google Patents

Description

The invention relates to storage devices.

Known devices for control.

^; memory containing block memory, blocking schemes, correction schemes, comparison unit, comparator, generator, parity byte generator, parity byte control £ ΐ "^.

A disadvantage of this device is that a multi-digit control code is needed for monitoring and restoring, and the information from the memory goes to the first and second equal channels of corrections, which are twice the redundant equipment, after which the information is compared with each other at the output of these blocks correction.

The closest technical solution to the invention is a device for monitoring RAM, containing a number register, a modulo two convolution unit, a control unit, a comparison circuit and a local control unit, the direct information outputs of the number register being connected to the unit inputs convolutions on my

. I do two, the output of which is connected by the first inputs of the comparison circuit and the local control unit, the second and 30

the third inputs of which are connected ¹ respectively to the first and second outputs of the control unit, and the output is connected to the control input of the number register, the direct control output of which is connected to the second input of the comparison circuit, the inputs of the number register are connected to the inputs of the device [2].

A disadvantage of this device is that, having a device for controlling information modulo two, it does not ensure the recovery of information in the presence of a malfunction in any particular discharge of RAM cells. This reduces the reliability of the device.

The purpose of the invention is to increase the reliability of the device.

This goal is achieved in that the device contains a trigger, an element And a switch, and the output of the comparison circuit is connected to the first input of the element And, the single input of the trigger and the input of the control unit, the third and fourth outputs of which are connected respectively to the second input of the element X and the zero input of the trigger whose single output is connected to the third input of the element

758260

TH, the output of which is connected to the control output of the device, the trigger outputs are connected to one of the inputs of the switch, the other inputs of which are “connected” to the inverse control and information outputs $

register numbers, and the outputs are connected to the information outputs of the device.

The drawing shows a functional block diagram of the device.

The device contains a convolution unit 1 modulo two, a register 2 numbers having a trigger 3 control bits, a local control unit 4 serving to convert the control bits, a circuit, 5, a control block 6, which includes the decoder ’5. 7 modes. The inputs of the device are connected to a block of controlled RAM, consisting of registers. ra 8 addresses and storage 9.

The device also contains a trigger 20 10 ', which serves for inverse recording, a switch 11, consisting of bit switches 12, each of which contains an element AND 13 and 14 and an "element OR 15. The device also includes 25

. element 16 also enters. The accumulator 9 has information outputs 17 and information, inputs 18. The output of element 16 is connected to the control output 19 of the device. 20

Direct information outlets PE _x

'Gistr 2 is connected to the inputs of block 1, the output of which is connected to the first inputs of the comparison circuit 5 and block 4, the second and third inputs of which 25 are connected respectively to the first and second outputs of block 6, and the output is connected to the control input of the register 2, direct control output which. pogo connected to the second input of the circuit 5 comparison. Output of circuit 5 compared to 40

"Nenii connected to the first input element And 16, a single trigger input ·

10 and the input of block 6, the third and fourth outputs of which are connected, respectively, with the second input of element 45 AND 16 and zero of the trigger input 10,

'/' "the unit output of which is connected to the third input of the element AND 16.

The outputs of the trigger 10 are connected to one of the inputs of the switch 11, the other inputs of which are connected to the inverse control and information outputs of the register 2, and the outputs of the switch,

11 are connected to the informational outputs of the device.- '·;? ·' ·

The device works as follows. , ..

. In the cycle of writing data to the drive 9. information from external devices on inputs 18 is initially entered into register 2 and using block 1 convolution-60 ky modulo two, its parity check code is generated, which is fed to the input of the block

4. ’’ If there is a “record” control signal at the other input of the block 4.

the parity code from the output of this block is written to trigger 3 of the check digit. Further, information from the forward and reverse information outputs of register 2 and the parity code from the forward and reverse control 'outputs of register .2 arrive at the input of the switch 11 for recording into the cell of the drive 9, whose address is set on the register 8 of the address. In the initial state, the trigger 10 is in the zero state, while the enabling signal from the zero output of this trigger ensures the passage of direct information from the corresponding outputs of register 2, and the inhibit signal at the single output prevents the passage of feedback information from the inverse outputs of register 2. Thus, the direct information Register 2 passes through the element And 13 and the elements OR 15 of the switch 11 and is recorded in the cell of the drive 9 with the address set on the register 8 of the address.

In the reading cycle, after the read information from the specified cell of the drive 9 is entered into register 2, in comparison circuit 5, its control begins by comparing the code at the output of modulo two convolution unit 1 (which is the parity code of the information received in register 2) with the code parity on the direct control output of the register 2. In the case of a mismatch of these codes, the parity at the output of the comparison circuit 5 has appeared. There is a signal of non-comparison, which establishes the trigger 10 in one state, issues a command to the control block b to organize re-recording of the received information to the cell of the drive 9 with the address present in address register 8, and simultaneously enters the input of the AND element

16. However, the signal. "RAM failure" at the output of the element And 16 does not appear, because the control b tree at the first non-comparison signal from the comparison circuit 5 does not give an output permit signal. The specified signal is issued by the control unit 6 in the presence at its input of the repeated signal of incomparability from the comparison circuit 5. Thus, the Organization of the re-recording of the received information in the same cell of the drive 9 occurs, but taking into account the feature described below. The signal "Record" at the input of block 4, the parity code received on the register 2 information is similarly written to the trigger 3 of the check digit and, together with the information of the register 2, goes to the corresponding inputs of the switches 11. Given that the trigger 10 is set to one, the enabling signal is now already with a single output ----- ".

'5 758260

Yes, this trigger provides passage through the switch 11. Inverse information from the inverted outputs of register 2, and the signal from the zero output of trigger 10 prohibits the passage of direct information 5 from the direct outputs of register 2. Therefore, the reverse information from register 2 is recorded in the drive cell 9, the address of which is set earlier in the read mode from the address register 8. After the end of the write cycle, the information is returned, the device immediately re-reads this information in register 2. After writing the return information uu / 2 in the register ³ begins its inspection by comparing the parity code in the comparison circuit 5 described manner. In case of coincidence of the parity codes of the newly received reverse information and its received parity code, the circuit 5 20

comparisons in this repeated reading cycle do not produce an incomparability signal. Thus, the information; re-read from the specified cell of drive 9 is considered restored if there is a failure of the type “False ^ path”, or “False unit” in any one bit, or an odd number of bits of this cell, but is the inverse of the original information. 30 At the same time, information from register 2, when transmitted through information outputs 17, to external subscribers of the device, again goes to inputs

Switch 11 and, taking into account the single state of trigger 10, becomes the inverse of information recorded in register 2, and for external subscribers. This is direct information. On this cycle

₍ recovery of information in cell dd of drive 9 ends and control unit 6 outputs a reset signal to the initial zero state of trigger 10. If the re-read return information of cell d »of drive 9 does not coincide with its accepted parity code, the comparison circuit 5 generates a repeated non-compare signal at its output, according to which the control unit 6 issues on the __ output permission for the passage of the signal "RAM Failure" from the output 19 of the element 16.

The described device performs information recovery in the event of a malfunction in any single discharge of any RAM cells by inverting this information and re-writing and reading.

Claims (2)

Claim A device for controlling RAM, containing a number register, a convolution unit modulo dya, a control unit, a comparison circuit and a local control unit, the direct information outputs of the number register are connected to the inputs of the convolution unit modulo two, whose output is connected to the first inputs of the comparison circuit and local control unit, the second and third inputs of which are connected respectively to the first and second outputs of the control unit, and the output is connected to the control input of the number register, the direct control output of which is under It is connected to the second input of the comparison circuit, the inputs of the number register are connected to the inputs of the device, which is different from the fact that, in order to increase the reliability of the device, it contains a trigger, an And element and a switch, and the output of the comparison circuit is connected to the first input of the And element, unit trigger input and control unit input, the third and fourth outputs of which are connected respectively to the second input of the element And and the zero input of the trigger, the single output of which is connected to the third input of the element And, the output of which is connected to the control at the output device outputs a trigger coupled to one of the switch inputs other vhodSch which are connected to inverted outputs of the control information and the register number, and the switch outputs are connected to data outputs of the device. Sources. Information taken into account in the examination 1. US patent No. 3949208, cl. 235-153, published. 1976. 2. USSR author's certificate. No. 333559, cl. “, 1 C 29/00, 1970 (prototype). 758260 49