SU742948A1 - Cascade processor for spectral processing of signals - Google Patents

Description

The invention relates to computing and B can be used in various digital computing information processing systems. The known cascade device of the fast Fourier transform, containing AND blocks of memory, connected sequentially, and arithmetic blocks, each of which is connected by an input (output) with a velocity (input) of the corresponding memory block l. The closest in technical essence and the achieved result to the invention is a cascade processor containing VI arithmetic blocks, two groups of Y sequential access memory blocks, i-th sequential access memory blocks, respectively, connected to the inputs of the i -th arithmetic unit, whose outputs connected to the first inputs of (it-1) -th sequential access memory blocks, the output of the i-ro arithmetic unit is connected to the third input of the (i + 1) -th arithmetic unit, the fourth input of the i -th arithmetic unit a is an input for the input of constants, while the inputs of the first memory block and the third input of the first arithmetic unit are connected to the input of processor 2. The disadvantage of these devices is the narrow functionality, which is as follows; their structure is designed for a single length of the original array, which significantly reduces the applicability of such processors; input of the initial array of information and output of the result array is carried out in different order of the operands of the arrays, which, with considerable speed of the cascade processors, is poured into additional equipment for reindexing the arrays; the inability on the same equipment to perform weight processing and refinement of the correlation functions. The purpose of the invention is the expansion of functionality due to the computation of corporate functions, as well as due to the possibility of input and output of information in any order.

This is achieved by the fact that in a cascade processor of spectral signal processing, containing And arithmetic blocks, two groups of and sequential access memory blocks, the outputs -i -k of the sequential memory blocks of the first and second groups of the first and second groups are connected to the first and second inputs 1 - arithmic unit, the first and second outputs of which (except connected to the first inputs (i ii) -K of the sequential access memory blocks of the first and second groups, respectively, the third output of the r-th arithmetic unit except (I-1) -th and.rifmeti ggeskih-blocks connected to the third input

(fl) -ro of the arithmetic unit, the third Input of the first arithmetic flea is connected to the input of the input of process constants, a switch, an arbitrary access memory block, an index memory block are entered,

1 a group of Y memory access blocks, with the input of the processor constants connected to the serial inputs of the () s sequential access memory blocks of the third group whose outputs are connected respectively to their second inputs and to the fourth inputs of the {-itl-x arithmetic blocks, the first output of the random access memory block is connected via (I-1) th random access memory block of the third group with the first input of the switch, through the nth random access memory block of the third group with the second input of the switch and directly with the third input of the Y th arithmetic unit, the first and second outputs of which are connected respectively to the first and second random access memory blocks and the first and second outputs of the processor, the third output of the random memory block —isjcryii is connected to the second input VI th sequential memory block in the access. of the third group, to the fourth input of the I-th arithmetical block to the third-off input of the switch, the output of which is the third output of the processor, the first to the second output of the first arithmetic block are connected to the second inputs Kj of the sequential access memory blocks of the first and second groups, respectively, and its fourth The input is the input to the processor.

The drawing shows the block diagram of the helmet: 1kkogo processor spectral signal processing.

The processor contains arithmetic basques .1, blocks. 2, 3 and 4 sequential access memory, block 5 of proiKEcau iorx access memory, switch 6, shadek: ... ;; block 7 5 input 8 of the processor, input 9;: i :: Cv- a processor xxag, outputs 1O,, 1 i;:. 1.2 Processor ... The reduced variable is a structure ;; the mountains are designed for s & a stallia for the raw array in H 64 points.

 The processor has the following

 city / cCj-OtiSOfvI

The input 8 to the processor is supplied by the xesod: mass of the mass; w, which is multiplied by the first arithmetic unit and the iffywaiMK input constants received at input 9 1 of the same input 9 during the weighing process in the first arithmetic unit to the processor .a, eni direct l.kbo obraytnogo Fourier transform. These coksk you come in a tank of 4 paiyjETH sequential access.

Result Besa processing in the first arithmetic unit on the first and second. The output of this block is distributed in the corresponding boot of a two-second memory stick, the half-timer of the total access. The order of receipt of the elements (individual operands); 4C51 one array can be any , E, including the maximum possible flow in natural order. In what block of memory from the 3rd and 4th group the next operands will be recorded are determined by the blocks: of the entire device, which is not shown in the drawing. For that reason, the processor could proceed to its mainline; in its memory blocks. there must be the initial array itself (or the mind of the soul:; nd for the weight function)% Cic), k Oz1.- ,. N-1 and an array of constas (j -; p -), K.-O, M - 1 Bloa 5 lt t ;;;: access for accessing under control of index b.1oka rnciffpesTKo records: - intermediate results and. Gives them to last arif 1et41che (31st unit 1c

f.5osg, dx8 others, and block 4 of memory successively x), together with switchboard 6, ensure the output of the result (the discrete Fourier spectrum) in the natural sequence.

Claims (2)

If necessary, a mutually correlated function requires a requirement; -;: ht computation; direct discrete Fourier transform, multiply the result by the reference spectrum and finally perform the inverse discrete Fourier transform of the product. Thus, the result from intermediate outputs 10, 11 can be immediately input to input 8 and input through the first arithmetic device, which by this time has finished its work on the direct discrete Fourier transform (first stage). At the second stage, this arithmetic unit will multiply the result of the first stage by the reference spectrum and the control unit will spread out production into the corresponding memory blocks of the second group. Further, the processor provides an inverse discrete Fourier transform. The autocorrelation function is calculated in the same way, only at the beginning of the second ethane of calculations, the first arithmetic unit of each complex value in the result array of the first stage determines the module. A cascade processor can also operate with smaller arrays of source information. If the processor contains T arithmetic units, then this means the maximum size of the array of complex numbers with which it can work is equal. In the case of submission to it in a smaller array, it is distributed by the control unit into the higher memory blocks of the second group (the beginning of the block count from the input nponisccopa). The operation of the processor in this case, according to the implementation of the Fourier fast transform algorithm, lasts as many times as fast as the initial array is less than the maximum that the cascade processor is designed for. Thus, the invention makes it possible to significantly expand the functional capabilities of a cascade processor on the same equipment. A cascade processor can calculate the spectrum and correlation functions with any, array of initial information not exceeding, where Щ is the number of stages in the processor. Input and output information is provided in the processor in a natural order. Expanding the functionality of a cascade spectral signal processor allows for a wider range of applications. The invention of the cascade processor of spectral signal processing, containing p arithmetic blocks, two groups of AND blocks of sequential access memory, outputs of i-X blocks of sequential access memory of the first and second groups are connected respectively to the first and second inputs of the i -th arithmetic block , the first and second outputs of each (except I-go) are connected to the first inputs of (i +1) -th memory blocks of sequential access, respectively, of the first and second groups, the third output of the i -th arithmetic unit, except (nl) -ro arithmetic eskih blocks connected to the third input (i +1) th arithmetic unit, a third input of the first arithmetic unit connected to the input processor input constants, characterized in that. in order to extend the functionality by calculating the correlation functions, as well as by the possibility of entering and outputting information in any order, a switch, a random access memory block, an index memory block, a third group of I sequential memory blocks are entered into it access, the input of the input constants of the processor is connected to the first input of the (h-2) -x sequential access memory blocks of the third group, the outputs of which are connected respectively to their second inputs; And to the fourth inputs () x arithmetic their blocks, the first output of the random access memory block is connected via (n -1) th random access memory block of the third group to the first input of the switch, through the 7th random access memory block of the third group to the second input of the switch and directly to the third input and th arithmetic unit, the first and the second outputs of which are connected. respectively, with the first and second inputs of the random access memory and with the first and second outputs of the processor, the third output of the memory block of an arbitrary power supply is connected to the second input / | -th block of the sequential access of the third group, to the fourth input of the h-ro and the metric block and to the third input of the switch, the output of which is the third output of the processor, the first and second outputs of the first arithmetic. units are connected to the second inputs of the sequential access memory blocks, respectively, the first and second groups 77429488 1W, and its fourth input is input1. U.S. Patent 3,816,729 iqjoueccofja.kl. G 06 F 15/34, 1974. Information sources, 2. Foreign electronics, Arik Gyeh into account when expertiseN 8, 1975 (prototype). .