SU378826A1 - RANDOM NUMBER GENERATOR - Google Patents

Description

one

This invention relates to the field of instrumental investigation of random processes by statistical testing.

iB is currently used by pseudo-random numbers produced by a digital computer in the OS. However, to obtain them, a significant expenditure of machine time is required, which leads to a decrease in the efficiency of the use of digital computers and, most importantly, to a loss of the real time scale in the numerical simulation of complex systems.

The proposed generator based on the inverse function method, in which a functional transformation based on the piecewise linear approximation of the distribution — F (x) —is used to derive random numbers according to an arbitrary distribution law to obtain a sequence of random numbers with a given distribution law. In this case, the range of possible values of x is divided into n equal intervals.

The known random number generators (RNG) with a given distribution law, based on the method of inverse functions, differ from each other by the method of finding the interval and, consequently, by the speed and volume of the equipment. You can select RNG with parallel, sequential and logarithmic methods of finding the interval. In the RNG, with logarithmic enumeration, the interval is searched in t + 1 cycles, where m is the binary number of the number Xj, i.e. n 2.

The proposed random number generator is based on the inverse fundi method with a logarithmic interval search method, in which the required interval is searched not in cycles, as in the known RNG with logarithmic enumeration, but at the same clock rate. This allows you to double the number of splitting intervals which significantly increases the accuracy of the functional conversion. In addition, the RNG structural scheme is somewhat simplified due to the absence of a delay circuit, which greatly simplifies the configuration of the generator.

FIG. 1 shows the block diagram of the proposed RNG with the formation of random

numbers according to an arbitrary law of distribution by the method of logarithmic enumeration per t clocks; on. FIG. 2 is a diagram of a specialized descrambler. The generator contains a generator / uniformly distributed random numbers, a digital comparison circuit 2, a persistent storage device 3, a clock generator 4, a specialized decoder 5, a random number generation register 6, input 7

and output 8 valves. The inputs of the formation register of the random number Xg through one input of the input valves 7 are connected to the outputs of the clock generator 4, and through the second to the outputs of the digital comparison circuit 2, one input of which is connected to the generator output of uniformly distributed random numbers g and the second input to the output a constant breaking device (ROM) 3. The outputs of register 6 on the one hand are connected via a dedicated decoder for logarithmic search to the inputs of the ROM 5, on the other hand they are connected to one input of output gates 8, each e inputs of which are connected to one output of beats generator 4. The generator operates as follows. The start-up pulses from the digital computer are fed to the clock generator 4, which generates a series of pulses, the number of which is determined by the number of logarithmic steps. The pulses are taken from different buses m log2. The beginning of the logarithmic search always starts from the middle of the split area, so the first impulse of the clock generator output goes directly to ROM 3 and selects the middle split of the split area Xg - that goes to one of the digital comparison circuit 2 This same pulse arrives at one of the inputs of the input valves, to the second inputs of which the result of a comparison of a uniformly distributed random number given by the generator / evenly distributed random numbers at the command of the clock generator 4 and the middle value of the partition area Xi -. When l (register 6 is set by the input valve 7 to the homing state. This means that the further search will go to the left. With () the register 6 2 y is set to one (the further search goes to the right). Thus, the setting, register 6 in the necessary state is produced by the first pulse of the generator. cycles. Information about the state of the register 6 goes to the decoder 5, which is executed in the form of separate blocks (D, D ..., Dm-t), each of which is one step of logarithmic iteration (see Fig. 2). The second pulse of the clock generator enters one of the inputs of the Input gates of the register 6 and reads from the decoder 5 one of the values of the partitioning area - or depending on the state of the register 6. The signal from the decoder 5 selects from ROM 3 the value of the distribution function or 4 / P / 3n f) depending on the direction of logarithmic brute force. The result of comparing this value with a uniformly distributed random number g sets register 6 to the single or zero state. Register status information is sent to all decoder blocks, starting from block 2 Similarly, the remaining register triggers are set, the th pulse of clock generator 4 reads the decoder value from the D-m-i block of the last search step, which selects from the ROM 3 the value of the distribution function of this argument. The result of comparing this value with a uniformly distributed random number sets the last trigger of register 6 to the desired state. The same clock pulse is applied to the second inputs of the output gates and thereby reads from them a random number Xr distributed according to a given law. (I). The subject of the invention is a random number generator containing a register. OUTPUTS of which are connected to the first input of the comparison circuit through a decoder and a persistent storage device whose second input is connected to the output of a generator of uniformly distributed random numbers whose input is connected to the first clock output of the clock generator and the first input block of input valves, the other inputs of which are connected to the corresponding outputs of the clock, the last clock output of which is connected to the Output valve, characterized in that, in order to expand the class of tasks, the corresponding inputs of the logarithm decoder are connected to the inputs of the output valve unit, the outputs of the input valve unit are connected to the register inputs, the comparison circuit outputs are connected to the corresponding inputs of the input valve unit, the input of the permanent storage device is connected to the first clock output of the clock generator.

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