TW265496B - Time-sharing multi-tasking digital filter and signal processing method thereof - Google Patents

Abstract

A digital filter, that processes input signal with time-sharing multi-tasking and has M input ends and M output ends and one control signal, comprises: 1. multiple pipelined registers, among which those N pipelined registers are one sequences in which any one input end of the second to the Nth register is connected to output end of its former pipelined register in sequences; the structure of the above pipelined register is in one sequence with M unit delay devices, in which any one input end of the second to the Mth unit delay device is connected to output end of its former delay device in sequences; one clock signal is connected to all unit delay devices in the above N pipelined registers; 2. multiple feedback multiplier, each multiplier has its own multiplier and with input end signal as multiplicand; the above N feedback multipliers are in one sequence, in which any one input end of the first to the Nth unit feedback multiplier is connected to output end of corresponding the first to the Nth pipelined registers; 3. one Mx1 multiplier with M input end of digital filter as input end, and by utilizing the above control signal to select one of them as output signal; 4. one first adder, in which one input end of multiplexer and output end of the above N feedback multiplier separately are connected to N+1 input ends of the first adder; the above input end of the first adder is connected to input end of the above first pipelined register; 5. multiple positive multiplier, each multiplier has its own multiplier and with input end signal as multiplicand; the above N feedback multipliers are in one sequence, in which any one input end of the first to the Nth positive multiplier is connected to input end of the corresponding first to the Nth pipelined registers; input end of the N+1th positive multiplier is connected to output end of the above Nth pipelined register; 6. one second adder, in which N+1 input ends of the second adder separately are connected to the above corresponding N+1 positive multiplier; 7. one 1xM demultiplexer with input end of the second adder as input end, and by utilizing the above control signal to select one output ends among N demultiplexers output ends as output signal.