SU674211A1 - Pulse selector - Google Patents

Description

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The invention relates to the field of automation and computing. The selector can be used to protect digital devices from impulse noise.

Selectors are known that contain three elements of coincidence, a delay line, three inverters, an element OR 1.

These selectors are complex, pulses and their output are characterized by instability of parameters.

The closest to the proposed is a selector containing an inverter, two IS-NE elements, an RS flip-flop, a storage capacitor, two diodes 2. The capacitor value is selected so that it recharges. It is less than the duration of the useful signal. Noise pulses, the duration of which is shorter than the recharge time of the capacitor, are not passed to the output of the selector. This device allows the selection of pulses of any polarity and ensures a good steepness of the pulse front.

However, the presence of one capacitor in the high and low level selection pulse chains opens the way for short pulses from one circuit to another. When the input signal changes from a low to high level, a low level pulse signal rushes in two ways: a low level is fed through the inverter, and a short positive pulse passes through the parasitic capacitance of the diode of the high level pulse selection circuit. This pulse is ahead of the signal transmitted through the inverter, and is added to the potential accumulated on the capacitor during the action at the low level input. The amplitude of the additional pulse depends on the parasitic capacitance of the diode and is 0.5-0.9 V, and the duration is not.

If during the action at the input of the low-level pulse selector a capacitor accumulated in the capacitor, insufficient to switch the trigger to a state corresponding to the low level at the input of the selector, but the sum of this potential and additional pulse exceeds the threshold level of the logical unit, then the trigger does occur . This leads to a decrease in the pulse selection threshold.

low level The degree of efficiency depends on the ratio of the threshold level of the logical unit lUi and is polyclic of the incremental impulse. In practice, the threshold for selecting low level pulses is more than 25% lower than the threshold for selecting high level pulses.

The selection threshold of low-level pulses in the H.iiiecTHOM selector is determined not only by the value of the selector capacitance, and the parasitic parameters of its elements, so it does not become (billet and cannot be set to the required value with sufficient accuracy. high and low level pulses. In this case, the specified selector is not suitable.

The aim of the invention is to improve the accuracy of setting the same thresholds for the selection of pulses of low and high levels.

To achieve this goal, a selector containing an inverter, two NAND elements, an RS flip-flop, inputs connected to the outputs of the NAND elements, a storage capacitor connected between the first inputs of the AND elements, and NO, and two diodes cathodes connected respectively to the input and output of the inverter, and the anodes, respectively, with the first inputs of the NAND elements, an additional inverter is introduced, the input of which is connected to these input signals and the second input of one AND-NOT element, while the second input of the other element IS-NOT & to exit extra An additional inverter and the input of the main inverter.

The drawing shows a schematic diagram of the selector.

The selector contains an inverter I ,, elements И-liE 2 and 3, which are matching elements, trigger 4 on logic elements 5 and 6, storage capacitor 7, diodes 8 and 9, additional inverter W.

In the initial state, the selector has a low voltage level at the input bus II, a high voltage level at the anode of diode 8, and a low voltage level at the anode of diode 9. Consequently, on the output bus 12 selector - zero.

When a single level impulse arrives at the input bus, a low voltage level appears at the output of the inverter 10, a unit level remains at the output of the element 3 and the accumulator capacitor 7 is recharged. When the voltage at the anode of the diode 9 reaches the threshold level , but the output of which is set Y} X) is the voltage, the trigger 4 overturns and a single level appears on the output type 12 of the selector. By the action of the impulse of the single U | H), the input bus selector a low voltage level, which closes member 3, its output usta1gavlivaets high voltage level. Element 2 remains closed because a low voltage level is established at the anode of diode 8 because the capacitor 7 plate, connected to the anode of diode 8, has a low voltage level. At the outputs of the matching elements 2 and 3, the unit levels are set, therefore trigger 4 retains its previous steady state. At the exit / shoi tine 12 selector - a single level.

Subsequently, capacitor 7 is recharged. The potential at the apode of diode 9 decreases to a low voltage level, and the potential at the anode of diode 8 increases, and upon reaching the logic threshold, element 2 opens, and trigger 4 overturns. A voltage level is set on the output selector bus. Consequently, the recharge time of the storage capacitor 7 determines the magnitude of the threshold for the selection of pulses of both low and high voltage levels. Impulse noise, the duration of which is less than the selection threshold, does not pass through the selector. The duration of the useful signals is greater than the value of the selection threshold, therefore, the selector transmits the useful pulses of high and low voltage levels without changing their duration.

Claims (2)

1. USSR author's certificate number 444317, cl. And 03 K 5/18, 07.28.72. 2. USSR author's certificate number 507922, cl. H 03 K 5/20, 32.10.74.