SU645259A1 - Pulse selector - Google Patents

Description

one

The invention relates to the field of automation and computer technology and can be used to protect digital devices from impulse noise.

Known pulse selector containing / 5-flip-flop, the inputs of which are connected to the outputs of the matching logic elements AND-NOT, the second inputs of which are connected to the anodes of the diodes, the input logic element AND IS, the capacitor 1.

However, this selector has an insufficient accuracy of setting the pulse selection threshold with a low level and does not allow setting the required upper and lower selection thresholds of different pulse durations of the high and low levels.

The purpose of the invention is to improve the accuracy of setting the pulse selection threshold and expand the functionality of the selector.

To do this, a pulse selector containing a 5-flip-flop, the inputs of which are connected to the outputs of matching logical elements AND-NOT, the second inputs of which are connected to the anodes of the diodes, the input logic element IS-NOT, a capacitor, a capacitor and two resistors connected by the same terminals cathodes of diodes, and others with the first inputs of their matching logic elements, which are interconnected via an AND – NOT input logic element, and the second inputs are connected via capacitors with a common bus power supply.

FIG. 1 is a diagram of the selector; in fig. 2 shows time diagrams of voltages at points a and f of the circuit.

The pulse selector contains the input

terminal /, input logic element AND- NOT 2, matching logic elements AND-NOT, 5-flip-flop 5, resistors b and 7, diodes 8 and 9, capacitors 10 vi 11 and output terminal 12, with the clamp / connected

with the first input of element 3 directly, and with the first input of element 4 through element 2, the outputs of elements 3 - 4 are connected with the inputs of the 5-flip-flop 5, the output of which is connected to the clamp 12, the second inputs of the elements 5 and 4 are connected with a common thickness through the capacitors 10 and 11, the first and second inputs of the element 3 are connected through a series-connected resistor 6 and a diode 8, and the same inputs

element 4 - through connected in series resistor 7 and diode 9.

The selector works as follows. In the initial state at the clip / selector there is a low potential, at

capacitor 10 - zero level, at the output of element 3 - high potential, and the capacitor // has a single level. At the same time at the output of the element 4 there is a low level, as a result, at the clip / 2 selector also a low level. With the arrival of a high potential at the terminal / pulse at the output of the element 3, the potential is kept high, since the capacitor 10 has a low potential, and at the output of the element 2 a low potential is established. The capacitor 11 is quickly discharged through the diode 9, the resistor 7 and the element 2, therefore a high potential is established at the output of the element 4. Therefore, the trigger 5 retains its previous steady state and a low potential is observed at its output.

The low potential at terminal 12 is maintained until the capacitor 10 is charged to the potential at which element 3 opens and a low potential appears at its output, which triggers trigger 5, setting a high potential at terminal 12. This steady state of the flip-flop 5 is maintained until the end of the action of the high potential pulse at the terminal /. Upon termination of this pulse, a low potential is established at terminal 1, which closes element 3, setting a high potential at its output.

The capacitor 10 is quickly discharged through the diode 8, the resistor 6, the clamp /. The trigger 5 maintains its steady state, and a high potential is present at the clamp 12.

The end of a high potential pulse at terminal 1 is the beginning of a low potential pulse. The low potential at the terminal / closes the element 2, and the potential at the output of the element remains high because the capacitor 1.1 has a low potential. The trigger 5 is in a steady state, a high potential is observed at the clamp 12.

. If a low potential pulse is present at terminal 1, the capacitor // is charged to the potential at which the element opens and a low potential is established at its output, which triggers trigger 5. At the terminal 12, a low potential is established. Trigger 5 is in steady state.

Capacitor 10 determines the delay time of the high potential output control pulse relative to the high potential input control pulse. Capacitor 11 determines the delay time of the low potential output control pulse relative to the low potential input control pulse.

In the proposed selector, the pulse duration at the output is kept the same as at the input, the pulse has a high steepness of the front, the parameters of the pulses at the output are stable. In addition, the selector does not affect the threshold voltage selection of pulses with a low voltage level and allows the selection of pulses of both levels irrespective of the difference of the selection threshold.

Claims (1)

1. USSR author's certificate No. 507922, cl. H 03 K 5/20, 1974. Fig.i