SU651412A1

SU651412A1 - Buffer storage

Info

Publication number: SU651412A1
Application number: SU772522180A
Authority: SU
Inventors: Александр Васильевич Шанин; Владимир Иванович Горин
Original assignee: Предприятие П/Я Г-4273
Priority date: 1977-09-09
Filing date: 1977-09-09
Publication date: 1979-03-05

Description

Изобретение относитс к вычислительной технике и предназначено дл использовани в качестве входных буферных регистров систем обработки информации.The invention relates to computing and is intended for use as input buffer registers of information processing systems.

Известно буферное запоминающее устройство БЗУ, содержащее разр дный статический регистр и логические элементы.The buffer memory of the BZU is known, which contains a static bit register and logic elements.

Такое БЗУ имеет простую структуру, но недостаточно надежно .Such BZU has a simple structure, but not reliable enough.

Из известных БЗУ наиболее близким по технической сущности к изобретению вл етс устройство, содержащее статический регистр и логические элементы 2.Of the known BZUs, the closest in technical essence to the invention is a device containing a static register and logic elements 2.

Это устройство отличаетс высокой надежностью работы, но содержит дополнительно два триггера и имеет сложную схему.This device is distinguished by high reliability of operation, but contains an additional two triggers and has a complex circuit.

Целью изобретени вл етс упрощение устройства при сохранении его высокой надежности .The aim of the invention is to simplify the device while maintaining its high reliability.

Дл достижени поставленной цели в БЗУ,содержащее статический регистр, один вход которого подключен к шине сброса, To achieve this goal in the BZU, containing a static register, one input of which is connected to the reset bus,

другие входы статического регистра съедйнены с выходами элементов И и со входами элемента ИЛИ-НЕ. Первые входы элементов И соединены с информационными щинами , выходы статистического регистра подключены ко входам первого элемента И-НЕ, введен второй элемент И-НЕ, входы которого соединены с выходамиГ первого элемента И-НЕ, и элементы ИЛИ-НЕ, а выход - со вторыми входами элементов И.other inputs of the static register are connected with the outputs of the AND elements and with the inputs of the element OR NOT. The first inputs of the AND elements are connected to informational cells, the outputs of the statistical register are connected to the inputs of the first AND-NOT element, a second AND-NOT element is entered, the inputs of which are connected to the outputs of the first AND-NOT element and the OR-NOT elements, and the output to the second the inputs of the elements I.

На чертеже представлена функциональна схема устройства.The drawing shows the functional diagram of the device.

Устройство содержит элементы И 1, статический регистр 2, элемент ИЛИ-НЕ 3, элементы И-НЕ 4, 5, шину сброса 6, информационные щины 7.The device contains elements AND 1, a static register 2, an element OR-NOT 3, elements AND-NOT 4, 5, a reset bus 6, informational information 7.

Работает устройство следующим образом.The device works as follows.

Claims

When a signal arrives at the resetting bus 6, all triggers of register 2 are set to the zero state, and the output potential of the NAND 4 generates a zero potential, which determines the unit potential at the output of the IS-NOT 5 (at this time, the output of the OR NOT 3 there is a single potential defined by the zeros on the signal lines of the device). From the output of element 5, a single potential opens elements And 1, preparing the device for recording. Input code in the form of unit-level pulses, post. # ;. vx-i- r 6514 .. jrt- .... : 3 Pa to the inputs of the And 1 elements, sets the corresponding bits of register 2 to one. With this. At the output of the element AND-NO 4, a single potential appears. However, the single potential at the output of the AND-NOT 5 element does not disappear, since it is maintained by the zero potential from the output of the OR-NOT 3 element. The zero potential at the output of the OR-NOT 3 element appears with the arrival of the first g of the code pulse and disappears with the end of the last code pulse (desynchronization of code pulses should not exceed the pulse duration). Thus, the signal from the output of element 5 ("zero at the output of the element IS-NOT 5) appears only after the recording process is completed, which ensures reliable recording of the input information. The proposed EFD has a high reliability of reception of the code word, which is achieved that the blocking signal is wired to the end of the last code pulse. In addition, the circuit BZU simplified. The invention contains a buffer memory containing a static register, one input of which is connected to the reset bar, other inputs of the static register are connected to the outputs of the AND elements and to the inputs of the OR-NOT element, the first inputs of the elements AND are connected to the information buses, the outputs of the static register are connected to the inputs The first NAND element, characterized in that, in order to simplify the device, the second NAND element is entered into it, the inputs of which are connected to the outputs of the first NAND element and the OR NONE element, and the output is from the V the primary inputs of the elements I. Sources of information taken into account during the examination 1. Germany, article no. 2217045, cl. G 11 C 19/00, 1973.

2. USSR author's certificate No. 511631, cl. G 11 C 19/00, 08.26.74.