SU571922A2 - Device for multichannel discrete automatic tuning of synchronization frequency - Google Patents

Description

a selection cap of alternating signals, gated inputs of which are connected to the transmitter, as well as a group equipped: the channel and channel comparison codes, and the group equipment consists of a collecting unit cascade, a memory, a hardware time sensor, an arithmetic unit and a control unit, The accumulated cascade is connected by inputs to the outputs of all stages of the allocation of alternating signs, and the output is connected to the control unit and the sensor readout input of the hardware time code, which is connected to the master input a non-generator, a memory unit with address inputs (they are connected to the outputs of the cascades of alternating sign changes and a control unit, information inputs and outputs are connected to the arithmetic unit and information inputs to the controllable outputs of the hardware time code sensor, and the arithmetic unit is also connected the control unit, the outputs of the hardware time sensor and the first inputs of the comparison stages cascades, which are connected to the outputs of the sensor codes n of the hardware time by the second inputs, and on the third input - to the control unit The 211 channel latching channel signal block was entered, where P is the number of channels in which the first and second information inputs are connected to the corresponding outputs of the comparison stages and separation / sign alternation cascades, and the Request and activation input of the 2 P channel unit. latching signals from 6 channels are connected, respectively, with the output of the control unit and the output of the master oscillator, and the information outputs and outputs of the 2-channel P channel channel signals of the channel condition are connected to the corresponding m inputs of the control unit. Each channel of the 2 I-channel block of ficative signals consists of two channels in the form of series-connected two-transistor shear resistors and a key block on, and the input of the 1 push-pull shift register is the corresponding information input 2 of the P-channel 6nojEa latching state signals channels, and clock and sipnals are fed to the first and second synchronizing inputs, respectively, directly and through the inverter, the first information output of the key block of each channel is the output with the corresponding output Go to the 2nd P-channel block for fixing the channel state signals to the input Setting the push-pull shift register of your channel, and the second information output {stitching unit of each previous KaHOha is connected to the information input of the key block of the last channel, while the input is Quarter It is the information input of the key block of the first channel, and the output of Osga ™ is the new second information output of the klock block of the last channel. FIG. Figure 1 shows the structural electrical circuit diagram of a device for multi-channel discrete auto-tuning of the synchronization frequency; in fig. 2 is a structural electrical circuit of a 2n channel block for capturing channel state signals. The device for multichannel discrete auto-tuning of the frequency of the synchronous circuit contains in each channel the limiter 1, connected to the selection stage 2 of alternating signs, the gated signals of which are connected to the master oscillator, as well as group equipment 4 and channel cascades 5 of code comparison, Group equipment 4 consists of collecting stage 6, block 7 of storing the sensor .8 of the hardware time code, the arithmetic unit 9 and the control unit 10, the collecting cascade 6 being connected by inputs to the outputs of the cascade sv1 dividing the sign of krperemen 2 ,. and an output with a control unit 1Q and a sensor input 8 of a hardware time code which is connected by a counting input. It is set by a generator 3, a unit 7 for storing by address inputs is connected to the outputs of stages 2 of the control sign alternation and a control 10, informational inputs and the outputs are connected to the arithmetic unit by 9 information inputs - with controlled outputs of the sensors & & 8 hardware time codes, and the arithmetic unit 9 is connected, in addition, with the control unit 1O, the sensor output 8 of the hardware time code and with the first inputs of the channel stages 5 of the code comparison, KOToptie the second inputs are connected to the outputs of the sensor 8 of the hardware time code, the third node control unit 1O, as well as a 2P channel fixation unit for channel state signals, where P is the number of channels, the first and second information inputs of which are connected to the corresponding outputs of stages 5, comparison of codes and stages 2 of the selection The input and the request and the clock input -2Panal block 11 for latching the signals of the state of the channels are connected, respectively, to the output of the block 10 of the control and for the output of the latching state signals. channels are connected to the corresponding inputs of control block 1O. Each channel of the 2L-channel block 11 of the latching signals of the channel channels (see, Fig. 2) is made in the form of serially connected push-pull shift register 12 and key block 13, and the input Setting 1 of the push-pull shift register 12 is the corresponding information input 2Al - channel block 11, latching the signals of the state of the channels a to the first and second synchronizing inputs of it | (respectively, the clock signals were fed directly and through the inverter 14, the first information output of the key flea 13 of each channel, which was YOU By the move of the corresponding channel of the 2tl-channel block 11 of the latching of the status signals. Channel O4 is connected to the input Setting O of the push-pull register 12 to shift its channel, and the second information output of the key block 13 of each previous channel is connected to the data input of the key block 13 of the subsequent channel, while the input Request is the information input of the key block 13 of the first channel, and the output Stop is the second information output of the key block 13 of the last channel. The device operates as follows: Amplifier 1 and a cascade of 2 alternating alternating sign I in each channel allocate alternating signals received from the communication channel of the signals: privatized to one edge of the signal of the master oscillator 3 and converted into narrow pulses. These signals are combined by a collecting cascade. Bis of it is fed to a controlled input of the sensor 8 reading of the hardware time code, implemented in the form of a pulse maker, arriving at its counting input from the master oscillator 3. At the same time, the signals from the output of the cascades 2 at the inputs 2 of the P-channel block 11 for recording the signals of the state of the channels where they are memorized. The signaling accumulating stage 6 on the controlled outputs of the sensor 8 of the hardware time code forms the code group corresponding to the state of its discharge. This code group is fed to the recording inputs of block 7 memorized. At the same time, signals from the outputs of the stages of the selection 2 are changed for a selection of cell addresses of the storage unit 7 in which this code group is stored. To record the input information of each channel in the storage unit 7, a special zone is allocated. If there is no control signal on the gateway of the collecting stage 6; Emission, the exchange of information between the storage unit 7 and the arithmetic unit 9 is allowed, carried out according to the commands of the control unit Yu. The latter exchanges information at the moment only with one of the zones of the storage unit 7, the number of which is selected using the 2 P channel block 11 of latching channel state signals. The arithmetic unit 9 digitally performs all phase tracking operations, generating a correction signal and introducing a correction into the phase of the local clock frequency. Moreover, the execution and top-tuning of the local synchronization frequency is divided into two algorithms: according to the first algorithm, operations are carried out on tracking the phase and to work the correction signal, on the second - the phase correction itself. After executing the first algorithm, the unadjusted local synchronization code (in the form of a code group) is read from the arithmetic unit 9 (ta first vkoda channel channel 5 5 cp & codes of the corresponding channel, and intermediate results - in block 7 memorized and. If the code group recorded on the first inputs of the channel stage 5 of the code comparison, with the code value of the current hardware time at the output 15 of the corresponding channel through a pulse that corresponds to the sign of the local frequency s One time this impulse arrives at the corresponding first information 2P channel fixation block 11 of the channel status, where it is stored in the memory cell connected to this information input, C of the control 10 after executing one of the a signal is sent to the output. Request of a 2-channel block 11 for latching signals of channel states with the help of which a new channel is detected, where automatic tuning is possible, or where it is necessary to perform an algorithm for tracking the phase and generating a correction signal, Priet, on the corresponding information output 2 | 1 - Vloblo 11; the latching of the channel state signals appears CHrv nal, which is fixed by the control unit Yu & If the output signal of a 2P channel block i 1 of latching channel state signals appears at the information output that corresponds to the second group of the form. input inputs, then the control unit Yu

forms a command, by which the arithmetic unit 9 compares the phases of the local synchronization frequency and the signal received from the communication channel, generates a correction signal in the form of a code group according to a given algorithm, after which all intermediate results are read into the memory unit 7.

After executing this algorithm, the unadjusted code of the local synchronization frequency is read from the arithmetic unit 9 to the first inputs of the channel helmet and 5 to compare the codes according to the signal from the control unit 1O.

If the output signal of the 2P channel fixation unit 5 of the signaling conditioner appears at the information output that corresponds to the first group of information inputs, then the control unit 10 generates a command that corrects the phase of the | ijecKHfi blsac 9; the local synchronization frequency of that quan, whose number corresponds to the output of your 2-channel signal of 11 phyum & shsh signals is the state of channels. After completing the phase correction algorithm, the corrected code of the local clock frequency is read from the arithmetic unit 9 into the memory unit 7 and is then used as an intermediate solution in subsequent auto-tuning cycles.

If at the moment of arrival of the signal on the HIPP Request for a 2P-channel block of fixing signals of the states of channels 11, no information input was received by the TVforma, then a signal appears on the Stop. According to this signal, the control unit 10 is set to the mode of continuously issuing a request signal before appearing at least on one of the information inputs of 21 | 1-channel block 11 of the fsishysh signals from Tche $ gan channels, a signal from the output of one of the channel stages S code comparison S1I cascade 2 selection alternates. In the IGOM mode of constant request, the program does not execute an auto-tuning program (the arithmetic unit 9 is free).

The output signal from master oscillator 3 is used on 2 h-channel BLV 11 latching channel state signals as a clock signal when registering and erasing input signals.

When one of the inputs 16 and 17 (for example, to the input 16 of the first channel) receives a signal from the output of the channel stage 5, it compares the codes to the first memory element of the two-stroke register 12 shift of the record

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The unit, which is followed by the next half-wave signal from the master oscillator 3, passing through the inverter 14, is also recorded in the second memory element, which controls the key unit 13, When the request signal arrives at the information input from the control unit 10. mutates either to the first information output 18 of the key unit 13, if one is recorded in the push-pull shift register 12, or to its second information output, if zero is recorded in the push-pull shift register 12, the request signal arriving at the information input of the key block 13 of the next channel , polls its condition,

Thus, the request signal, connected to one of the information shields 18 or 19 2 of the I-channel block 11, for channel status signals is fed simultaneously to the control block 10 and to the input. Set O corresponds to its first memory element of the push-pull register shift 12 and the latter returns to the original (zero) (Permanent. The next half-wave signal from the output of the inverter 14 zero is written to the second memory element of the push-pull shift register 12. If in the push-pull registers 12 shift all the channels I write with zeros, then sshl cash from the input request is output stop 1 and the control unit 10. proceeds Last Request mode until arrival szagnala would although one of the information inputs 16 or 17 2li -katgalnogobloka 114 IEsatsii channel state signal.

If the synchronization frequencies of all channels are equal in nominal value, then in a 2} channel block. 11 latching of the status signals, the first information inputs 16 and the push-pull shift registers 12 and the key blocks 13 are not available. Therefore, if the input information received from the communication channels is equal to the synchronization frequency, the latching signal block 11 the state of the channels creates a sequence for processing each channel, and the block 10 controls the signals from the outputs I; the channel block if phgsavi from the channel states pnal expands the full program of adjustment without dividing ah into two algorithms.

The introduction of a block of fixing channel state signals will, by reducing the processing time of one channel, increase the number of channels served by 1.6-2.2 times. Formula for gaining 1. Device for multichannel and automatic auto-tuning of the frequency of synchronization. Yo aut. swith Nfc 431640, which means that, in order to increase the speed of auto-tuning, 21 channels are inserted, the channel state signaling block, where is the number of channels that have the first information inputs. with the corresponding outputs of the cascades of comparison of codes and cascades of allocation of Ziaxpermen, and the input Request and that; & the other input of the 211-channel fsss block of the channel state are connected respectively to the output of the control block of the outputs (. 9.-channel unit f The signals of the status of & subconnects correspond to the n input inputs of the control unit & laziness E. 2. The device according to claim 1, which is 2f (-quality block fixing the channel state signals is complete in the form of serially connected push-pull register and key block, with the input Set 1 of the push-pull shift register being with the corresponding information input of the 2H channel fixation signal of the channel state, and for the first and second synchronization Cie his inputs respectively filed t Direct signals directly and through an inverter, the first information output of the key block of each channel, which is the output of the corresponding channel of the 211-channel block for recording the signals of the channel state, is connected to the input Setting O of the push-pull shift register of its channel, and the second information line of the key block of each preceding the channel is connected with the information input of the key block of the last channel; the input Request is the information input of the key block of the first channel, and the output Stop - the second informational output of the key block of the last channel.

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