SU544157A1 - Device for synchronizing noise-like signals - Google Patents

Description

Ledova.; ejii: -; o connected switching node 9 and adders 1О and 11 to the corresponding UJiM inputs of multipliers 1 and 2.

The device works as follows.

The reference signals of the multipliers 1 and 2 (or; are merged by switching signals of a hereditary 8, having four phases O ° EO, 1ZO and 2 7O. The switching is carried out

the keys of the switching node 9, which are affected by the signals of the decoder 7 connected to the outputs of the n-th and (and - 1) -th stages of the generator 6 PSP. The phase values of the signals at the outputs of the adders 10 and 11 (respectively 1p and f) depending

from the state of the pth and (and - 1) -th cascades are given in the table.

In multipliers 1 and 2, the phases of the received and reference signals are subtracted and intermediate frequency signals are generated, which are fed to the error response determiner 3. To determine the discriminatory characteristic, we consider the ratios of the phases of the received and reference signals at different shifts in the temporary memory bandwidth delay. Let the delay of the received memory bandwidth and memory bandwidth at the output of the nth stage of the generator 6 memory bandwidths coincide. Then, for the upper channel in accordance with rows 1 and 2 of the table, the phase of the received signal is Fc 0, the phase of the local oscillator signal 8 1p takes the values O and 90 with a probability of 0.5, i.e. average value of f 45. The average phase of the intermediate frequency signal in the upper channel is ip 45.

For the lower channel, based on the same reasoning, we have φ 45. Phase difference

t PCB

the signals at the inputs of the error signal determiner 3 are O, the maximum positive voltage is generated at the output of the detector 3.

For the case of coincidence of the delay of the received signal with the delay of the SRP from the output of the (h - 1) -th stage of the generator 6 SRP we have: for rows 1 and 3 of the table: Ip О,

Pccp 315 ° - З ФпчА 315 °,

ipj 135; for rows 2 and 4 of the table:

FS - 180 °, (p ,, p, 1p „,, -45 °

 315 1 pfdv 135. The phase difference of the signals at the inputs of the determinant 3 in both cases is equal to 180, i.e. at the output of the error signal 3, the maximum negative voltage will be.

For intermediate delay values

of the received signal, the phase difference of the signals at the inputs of the determinant 3 will smoothly vary from 0 to 180. For the cosine characteristic of the error signal determiner 3, the voltage at its output is determined by the dependence

four&

° 7:

where UQ is the maximum voltage value at the output of the determinant 3; 6, ut-offset relative to the average position, tj is the duration of the elementary pulse of the SRP. For the prototype, U U (, (lt / t, i.e., the steepness of the characteristic at the zero point of the proposed device is twice as large as that of the prototype. Consequently, the synchronization accuracy can be improved.

An increase in the area under the discriminatory curve allows for a doubling of the search speed over a time delay, carried out both by smooth tracking, hook and discrete shift of the memory bandwidth, without increasing the likelihood of skipping synchronization mode.

Claims (1)

Invention Formula A device for synchronizing noise-like signals containing multipliers connected via a sequentially-connected error signal determiner, a filter and a clock generator with a pseudo-random sequence generator, characterized in that, in order to increase synchronization accuracy and reduce the time of searching for synchronism, the adders, a decoder, a switching node and the local oscillator, while the outputs of the decoder and the local oscillator are connected via series-connected switching node and adders to the corresponding the inputs of the multipliers, and the outputs of the pseudo-random sequence generator are connected to the corresponding inputs of the decoder. Sources of information taken into account in the examination: 1. Become a W.r. Gr-ififi-A Sotrasiboi of Binary Deeay-Lock Tracuing-Loop ImpBeineMta ЗЕ Тицй., V AES-E, Ju9, 1966, (prototype). A H 00 01 ten eleven L5jrz