SU799101A1 - Frequency synthesizer - Google Patents

Description

controllers JK -Tj lfrrep, KU triggers, logic 2-2I2IL, logical gates, and logic gates, with logic 2-2I2IL or connected between a phase detector and a variable division frequency divider, and the first R9 trigger between the unit for the difference frequency and reversible counter, the clock input of which is connected to the third output of a frequency divider with a fixed division factor through the first AND-NOT logic element connected to the forward output of the control 3is trigger, the inverse output of which is connected J - and K - inputs and to the fourth input of the logic element 2-I-2ILI, the third input of which is connected to the output of a frequency divider with variable division factor, while the first input of the logic element 2-2I-2IL is connected to the second input of the frequency divider a fixed division factor, and the second to the direct output of the controlling EC trigger, the clock input of which is connected through the second and third logical elements of the IS to the outputs of the unit to separate the difference frequency to which the S and the third RS are simultaneously connected tr googers and their direct outputs through the fourth logical element NAND are connected to the S input of the fourth RS trigger, the R input of which is connected to the output of the third NAND logical element, and the inverse output to the second input of the second logical element I- NOT and simultaneously with the R input of the controlling 31. trigger, the forward output of which is connected to the R inputs of the second and third triggers.

With this implementation of the frequency synthesizer, the first pulse from one of the outputs of the block for separating the difference frequency will cause the control ZK-trigger to activate, which will turn on the device for automatic searching and open the PLL, but so that instead of PDDD pulses, PDs start to receive auxiliary pulses second output DFCD shifted relative to the main by 180 °. This will lead to the fact that the FD will give the control voltage to the input of such a control voltage, which in synchronization mode would correspond to the capture of the PLL exactly in the middle of the FD characteristic, i.e. Simulation of the PLL ring in the synchronization mode will occur. In addition, the pulse input of the reversible counter now no longer receives a sequence of pulses monotonously decreasing in frequency, but a sequence of pulses from a third DFCD output. such

a constant frequency that would ensure the fastest possible rate for entering the synchronization mode for a given PLL system. Since in this case the device for auto search searches the second input of the VCO control voltage, which does not change smoothly, but in steps, then the moment will come when the ratio between the pulse frequencies at the DPKD and DPC outputs is reversed. At the same time, the first impulse from the second output of the unit for separation of the difference frequency (reverse impulse) will cause the control P1 to operate. -trigger that will enable the PLL and disable the auto search, i.e. it will be captured moreover, in the middle of the FD characteristics.

The drawing shows the functional diagram of the frequency synthesizer.

The frequency synthesizer contains OG 1 and VCO 2, the outputs of which are connected respectively to the inputs of DFCD 3 and DFCD 4. DFCD 3 has three outputs. The first is connected to one input of the PD 5, the second through a logic element b to the second input of the PD 5, and the third output through a logic element 7, switched by a signal from the direct output of the control Jk, the trigger 8, is connected to the clock input of the reversible counter 9. The output of PD 5 through the first LPF 10 is connected to the first inlet of the VCO 2. The PDKD 4 output is also connected to the second input of the PD 5 via a logic element b. The output of the PDD4 4 or the second output of the DFCD 3 to the second input of the FD 5 is also connected logical element b is implemented with the corresponding in control moves JK- -triggera 8. Yield DPKD 4 and a first outlet DFKD 3 furthermore connected to the inputs of block 11 for isolating the difference frequency. The outputs of the block 11, for allocating the difference frequency, are connected to the R - and S - inputs of the first R.3 trigger 12. to the S input of the second and third RS flip-flops 13 and 14 and to the inputs of the logic element 15. The outputs of the first US flip-flop 12 connected to the summation and subtraction inputs of the reversible counter 9. The direct outputs of the second and third RS triggers 13 and 14 are connected to the inputs of the logic element 16, the output of which is connected to the S input of the fourth trigger 17. The second and third RS triggers 13 and 14 , the logic element 16 and the fourth trigger 17 form a block for the allocation of imp the reverse pulse, which from the inverse output of the fourth RS-trigger 17 goes to the R-input of the controlling 3k-trigger 3 and to the input of the logic element 18. The output of the logic element 15 is connected to the R input of the fourth RS-trigger 17 and to the second input of the logical element 18, the output of which is connected to the clock input of the control ZKtrigger 8. R-inputs of the second and three. The other L5-triggers 13 and 14 are connected to the direct output of the controlling ZK-flip-flop 8. The output of each discharge of the reversible counter 9 is connected to the corresponding inputs of the DAC 19, which produces the control voltage and supplies it to the second input via the second low-pass filter 20 VCO 2. The frequency synthesizer works as follows. Suppose that at the initial time the frequency of the NCO 2, divided by the PDKD 4, differs from the frequency of the exhaust gas 1 divided by the DFCD 3. In this case, one of the outputs of the block 11 for selecting the difference frequency will receive a negative pulse, which through the logic elements 15 and 18 to the clock input of the controlling ZK-trigger 8 and overturn it to the position O at the inverse output. This O, arriving at the 3 - and - inputs of the controlling SQ-trigger 8, prohibits its activation from subsequent pulses of the difference frequency at the clock input, i.e., it self-locks. At the same time, O from the inverse output of 31 -thrigger 8 prohibits the passage of pulses from DPKD 4 through logic element 6 to the second input of PD 5, and 1 from the direct output of tJ K. -rigger 8 allows passing through logical element 6 to the second input of PD 5 pulses from the second DFCD output 3. The pulse frequencies from the first and second outputs of DFCD 3 are equal, in phase these pulses are shifted by 180 °. The pulses from the first DFCD 3 output form a sawtooth voltage PD 5, and the pulses from the second output, arriving at the second input of the PD 5, instead of pulses from the DPKD 4, form exactly B mid-phase characteristic into voltage frills, which are memorized by the memory circuit in PD 5 and through the low-pass filter 10 is supplied to the first input of the VCO 2. Thus, although the PLL is open (between the DPKD 4 output and the second input of the FD 5), the first input of the VCO 2 receives a control voltage from the output of the FD 5, as if corresponding to the capture of the PLL exactly in the middle of the phase characteristic EC tics. At the same time, 1 from the direct output of the LC to the trigger 8 allows the passage of pulses from the third output of the DFCD 3 through the logic element 7 to the clock input of the reversible counter 9, i.e., the device for the auto search. The operation of the reversible counter for addition or subtraction is determined by the potentials from the output of the RS-trigger of 12, which is set to a definite position by pulses from the outputs of the bLock 11 to isolate the difference frequency. A reversible counter 9 controls a DAC 19, generating, depending on the number of pulses received at the clock input, one or another gradation (step) of a constant voltage that goes to the second input of the VCO 2. Under the action of this step control voltage frequency The output of the VCO 2 is also discretely changed in the direction of decreasing the frequency difference at the outputs of DFCD 3 and DFCD 4. Since the frequency change occurs discretely, there comes a moment when the equal frequency point is passed to the reversible counter 9 enters the countdown team. This means that the Y.-trigger 12 under the action of the first negative pulse of the re-vers version from the other output of the block 11, in order to isolate the difference frequency, is tilted to the opposite state. At the very beginning, under the action of the first negative pulse from one of the outputs of block 11, one of the RS triggers 13 or 14 triggered to isolate the differential frequency. With the arrival of a negative pulse (reverse impulse) from the other output of block 11 to isolate the differential frequency, the second R6 -trigger 14 or 13. As a result, both inputs of the logic element 16 are received by 1 and a logic element 16 is sent O to S - the input of the T13-trigger 17. At the same time, the input of us-trigger 17 from the output of the logic element 15 will receive a positive impulse. Therefore, at the inverse output of the RS flip-flop 17, it is Wits O, which will prohibit the pulse from passing through the output of element 15 through element 18 to the Tac, input 3k. -trigger 8 and at the same time, this O, arriving at the R-input of the LC-trigger, 8, overturns the ei-o to the state O at the direct output. Logical O from the direct output of the AC. - trigger 8 will prohibit the passage of clock impulses from the third output of DFCD 3 through logic element 7 to the clock input of the reversible counter 9 (i.e., autosearch is turned off), set the RS triggers 13 and 14 to the initial state (i.e. O state on the direct outputs) and prohibits the passage of pulses from the second output of a DFCD 3 through the logic element 6 to the second input of the FD 5. Simultaneously 1 from the inverse output of the LC. - trigger 8 will allow the passage of pulses from the output of the DPCD 4 through the logic element b to the second input of the PD 5, i.e. the PLL closes and seizes in the middle of the characteristic of the phase detector, since now the phase shift between the pulses from the output of the PDCD 4 and the second DFCD 3 output is very small and does not exceed one

control steps

on the VCO 2.

Using this frequency synthesizer allows you to get the maximum speed, i.e., the minimum transition time from one frequency to another. This is one of the parameters of all frequency synthesizers and especially those used in devices where the carrier frequency all the time changes according to some law to improve the noise immunity, for example in devices that use the frequency adaptation method. Moreover, the capture is in the middle of the PD characteristic enables the most efficient use of the capture and retention band of the PLL, thereby ensuring high technological and. performance indicators of products in which this synthesizer is used. Capturing in the middle of the PD characteristic eliminates the possibility of synchronization failure due to interference.

Claims (2)

1.Galin A.S. The range of quartz stabilization of the microwave. M., Svy, 1976, p. 33. 2.Ryzhkov A.V. Combined PLL with reverse search. - Electroslap, 1975, No. 10, p. 6870 (prototype). Bxodi Woode