SU525157A1 - The method of accessing the storage device - Google Patents

Description

(54) METHOD FOR APPEALING TO STORING

Claims (2)

To the DEVICE if the jumpers of quince are magnetized in the direction coinciding with the direction of flow created by the address write current passing through the winding 10, the magnetized state of jumper c corresponds to the state Op, if the jumper 6 is demagnetized and the state O is demagnetized if the jumper CL is demagnetized. If the discharge current remagnells the core from state 1 to state 1p, i.e. produces a destruction, or magnetizes it along the flat part of the hysteresis loop into the Oh state, then on the output winding in an ideal two-hole core an interference with the same polarity as the output information signal should not be observed. However, since real cores do not have an ideal rectangular hysteresis loop, the cross sections Ct, B, and C are not ideally equal to each other, an interference current is induced on the leading edge of the discharge current, the amplitude of which is directly proportional to number of accumulator numbers. Therefore, in order to increase the reliability of the read amplifiers and the entire memory, the discharge current must be supplied before the address current by an amount sufficient to separate the time from the output information signal of the interference generated by the discharge current. Taking into account this factor, the time diagram of the operation of the charger according to the proposed method, carried out in FIG. 2, is performed. The storage device according to the proposed method operates as follows. Suppose that you need to select and regenerate information stored in the memory, for example, 1 number stores 10, 2 number - 11 3 number - 00, 4 number The first address current pulse that has a duration equal to or longer than the information reading time -1 T read formed by the valve 18 in the bus 13, passed through the polling tires 9 of the cores 1.5, reads the information 10 stored in them, switching the core 1 from the state 1p to the state Or. The discharge currents generated by the forma- tor 19, 20 in the windings 11 somewhat earlier than the first address current pulse in bus 13 do not affect the process of reading information from the cores 1.5, since jumper 0. is saturated in the direction coinciding with the direction of the flow created by the discharge current. The discharge currents, the passage through the windings 11, will switch the cores on which the previous sample has ended, from state 1 to state 1p. The output signal induced in bus 12 of the first discharge when reading 1p from core 1 enters the output of amplifier 21 by which it is amplified and outputted to output 23. Interferences generated in tires 12 on the leading edge of the discharge current are not amplified since gating is performed only during the first address polling pulse. The signal from output 23 enters the device for generating discharge currents in time and duration, which in FIG. 1 not shown. The second current address pulse, having a duration equal to or longer than the recording time information T T of the recording, formed by the valve 18 in the bus 13, does not change the state Op in the cores 1.5, The discharge currents during the second address pulse when accessing only the first number The charger may not be formed or formed, as shown in FIG. 2. The distributor 18 forms the first current current pulse in the bus 14, which passes through the buses 9 interrogating the cores 2, 6, reads the stored number 11, and the address buses 1O write the cores 1.5. Due to the fact that discharge currents flow through bit buses 11 that have an amplitude equal to or greater than the address current, cores 1.5 do not change their condition Op. On output buses 12 during the first address pulse, the output information signals only from 1p reading, which are amplified by an amplifier 21,22 and are output to the device for generating discharge currents. Then the distributor 18 generates a second address current pulse in the busbar 14, which passes through the tires 9 of the cores 2, 6, without changing their state Op, along the tires of the 10 cores 1.5, writes to that core, in which there is no discharge current in the bus 11. In this case, core 1 will be written 1, and core 5 will remain in the state Or. On output bus 12 from record 1, a reverse polarity signal will be induced compared to an information signal to which the read amplifier will not operate. Next, the distributor 18 generates the first address current pulse in the bus 15, which passes through the tires 9 interrogation of cores 3.7, reads the stored number of OOs, passes through the tires 10 cores 2, 6, without changing their state Or, as in tires 11 discharge currents flow. The discharge currents, formed somewhat earlier than the first current address pulse in bus 15, before reading the information, switch core 1 from state 1 to state 1p, without changing state Op of core 5. Then valve 18 forms a second address current pulse in bus 15, which passes through the tires 9 of the cores 3.7, without changing their condition Or, passes along the tires 10 of the cores 2.6, switching them to the state 1, since the discharge currents during the second address current do not pass through windings 11. Then the distributor 18 forms the first The address pulse, the current in the bus 16, which passes through the tires 9 of the cores 4.8, reads the stored number 01, passes through the tires 10 of the cores 3.7, their condition Op does not change, since in the tires 11 the discharge currents which, before the address current, switch the cores 2.6 from state 1 to state 1p. The output signal induced in the tires of the second discharge 12 is amplified by the amplifier 22 and from the output 24 enters the device for the formation of discharge currents. A co-ordinated current current pulse formed by the valve 18 in the bus 16 passes through the tires 9 cores 4.8, without changing their condition Op, passes through the tires 10 cores 3, 7 and also does not change their condition Op, as tires 11 discharge currents flow. Next, the distributor 18 forms the first current current pulse in the bus 17, which, passing through the buses 10 of the cores 4.8 of the last memory number, does not change their state Op, since discharge currents flow in the tires 11. The cores 3.7 of the action of the discharge currents do not change their conditions Op, since the previously read number of OOs was recorded in them. Then, the distributor 18 generates a second address current pulse in bus 17, which writes to the core 8 1 without changing the state of Op in the core 4, since discharge current flows from the former 19 in bus 11 of the first discharge. If the first number of the memory is accessed by the discharge current, the core 8 will be switched to the 1p state. Thus, in the memory of the proposed method, the sampling and regeneration of stored information was performed. TK can be seen from the operation of the storage device on the output buses 12 during the formation of the first current address pulses that produced reading information, only full-fledged information signals are present. The look at the timing diagram shown in FIG. 2, allows obtaining high reliability of the memory operation in the presence of low-frequency control circuits, low-frequency discharge current shapers having a falling front duration significantly longer than the allowed leading edge duration of the address current, producing information recording 1. When using high-frequency control circuits, high frequency current drivers, the timing diagram can be modified as shown in FIG. 3, by combining address and bit current pulses in one with a duration sufficient to read, write, and destroy information. Claims The method of accessing a memory device based on the recording and reading of information by a single current pulse, characterized in that, in order to increase the recording density and readability, an additional current pulse is applied during the recording and reading of information. 20 t d 15 18 17 eleven Cmpof 21 & ig.1 five job / s eight // 12 22 G24