SU447757A1 - Memory device - Google Patents

Description

one

The invention relates to a storage device (memory).

A memory device containing wideband ferroelectric piezotransformers is known, the input electrodes of which are connected to the corresponding numerical readout buses connected to the addressable read address shaper, the shielding electrodes to the readout digital buses. connected to the address writing driver, the output electrodes to the bit buses, one ends of which are connected to the corresponding read amplifiers, bit discharge drivers.

The known device has a lot of equipment, since it contains two bits of a recording driver for each bit, which is caused by the need to specify opposite directions of polarization of the piezotransformer material sections when recording information under the output electrodes.

The aim of the invention is to simplify the device, reduce hardware costs, increase its noise immunity.

This is achieved by the fact that the other ends of the bit buses of each bit are connected through resistors to the output of the corresponding bit shaper of the record.

The scheme of the proposed device is shown in the drawing.

The device contains a number of ferroelectric wideband piezotransformers 1

and two to two for each bit, which are storage elements. They are a monolithic structure consisting of piezoceramic plates 3 and 4 acoustically connected to each other through

the shielding electrode 5. The plates 3 are the excitation sections of the piezotransformers and the input electrodes 6 are deposited on their lower edges. The plates 4 are the generator sections and perform the function

the output electrodes 7 are deposited on their upper faces. Piezoceramic sections of the piezotransformer excitation sections of each discharge are rigidly polarized, and in opposite directions.

The input electrodes 6 are combined into readout lines 8, which are connected to the outputs of the addressable read drivers 9 having control outputs 10. Shielding electrodes 5 are combined

via addresses to the numeric write buses 11, which are connected to the outputs of the address write drivers 12 that have control inputs 13. The drivers 9 and 12 are controlled by the address decoder signals (in the drawing

not shown). The output electrodes 7 of the piezotransformers of each bit are combined into bit buses 14 and 15, one ends of which are connected via resistors 16 to the output of a corresponding bit writing recorder 17 with a control loop 18. Other ends of the bit buses are connected to the inputs of differential reading amplifiers 19 .

The device works as follows.

Information is recorded after all the storage elements of this address are transferred to the state "O, i.e., the information is erased."

When erasing the information in the selected address, the polarization voltage Up is applied to the corresponding numeric bus 11 from the address writer 12, and the discharge recorder 17 connects all the bit buses 14 and 15 to the common point of the device (zero potential is applied). Owing to this plate, 4 elements of the selected address are polarized in the direction corresponding to the entry "O.

In the recording mode, the voltage -Up / 2 is applied to the selected bus 11 from the output address writing driver 12, and 17 of those bits where the write 1 is written + f / p / 2, and where the write The bit buses are connected via bit write drivers 17 to a common point of the device. The common point is connected via address writers and unselected address rails 11.

In the selected address, the plate areas 4 of those elements, where the voltage -Up / 2 is applied to the electrodes 7, and the voltage -Up / 2 to the electrodes 5, are polarized in the direction of the corresponding record "1. This does not change the direction of polarization of the plate sections 4 of those elements of the selected address, where the electrodes 7 are connected to a common point, and the voltage -Up / 2 is applied to the electrodes 5, since the voltage difference between the electrodes 7 and 5 is equal to Up / 2 is not sufficient to re-polarize the plates 4, and these plates remain polarized in the direction specified when erasing information, i.e. in the direction corresponding to the entry "O. In the unselected addresses, the voltage difference between the electrodes 7 and 5 of the plates 4 does not exceed Up and the directions of their polarization do not change, i.e. there is no destruction or recording of false information.

When reading information shapers 12 connect the bus 11 to a common point. According to the address decoder signal from the output of the selected read driver 9, a voltage pulse is applied corresponding to the numerical band 8. As a result, the excitation plates 3 of the piezotransformers of the selected address are deformed. This deformation is transmitted to the generator plates 4, and at the output electrodes 7 in each discharge voltage polarized pulses appear, the polarity of which is determined by the direction of polarization of the piezoceramic sections of the generator sections, i.e. by the recorded information. The opposite polarity of the pulses in each discharge is due to the fact that the piezoceramic sections of the excitation section between the input and common electrodes have opposite polarization. These pulses are fed to bit buses 14 and 15 at the inputs of differential read amplifiers, and at their outputs, pulses appear, the polarity of which is determined by stored information.

The device provides non-destructive reading and unlimited storage of information with the power off.

Subject invention

A memory device containing ferroelectric transformers,

input electrodes of which are connected to corresponding readout digital buses connected to addressable read readers, shielding electrodes to digital write buses connected to addressable write drivers, output electrodes to discharge fields, one ends of which are connected to appropriate read amplifiers, bit write drivers, characterized in that, in order to simplify the device and increase its noise immunity, the other ends of the bit buses of each bit are connected via resistors to the output of the corresponding bit shaper recording.