JPH07201170A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To provide a semiconductor storage device capable of reducing noise at write time and securing operational margin of sense amplifier at the read time. CONSTITUTION:One sense amplifier SA is shared by two sets of bit line pairs, and precharge potential of a bit line BL is made the potential between the write potential of 'H' and 'L' for a memory cell C, and the data in the memory cell C are read out or written successively shifting time. In this dynamic semiconductor storage device, the activating order of the bit line BL is controlled so that the adjacent bit line pair writing later is arranged so as to hold the bit line BL connected to the memory cell C writing earlier therebetween among the memory cells C selected by the same word line WL.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device in which a plurality of bit line pairs share a smaller number of sense amplifiers.

[0002]

2. Description of the Related Art In recent years, as the capacity of semiconductor memory devices has increased, the size of memory cells has become smaller and the wiring intervals between bit lines have become narrower. For this reason, the noise due to the capacitive coupling between the bit lines cannot be ignored.

On the other hand, as the pitch of the bit lines becomes smaller, the pitch of the sense amplifier also becomes smaller. Therefore, in order to alleviate the pitch of the sense amplifier section, a method of sharing a sense amplifier by a plurality of bit line pairs has been proposed. There is. However, in this method, there is a problem in that the data written to the adjacent bit lines have different timings, and thus the data written first receives noise due to the potential amplitude of the bit lines written later.

This problem will be described with reference to the drawings. 7 is 4
This is a dynamic semiconductor memory device having a folded bit line configuration in which two bit lines are shared by one sense amplifier SA, and two of them are a pair of bit lines. In the figure, BL is a bit line, WL is a word line, C is a memory cell, SA is a sense amplifier, and P1 and P2 are control signal lines for connecting the bit line BL to the sense amplifier SA.

FIG. 8 is an operation waveform diagram in writing to the memory cells C0n and C1n when the word line WL1 is selected in this dynamic semiconductor memory device. Before the write operation is performed on the bit line BL,
It is precharged to two write potentials "1" and "0" for the memory cell C, that is, an intermediate potential Vcc / 2 just between Vcc and 0V. The sense amplifier SA is activated twice according to the data in the memory cells C0n and C1n, and the connection gates of the bit line BL and the sense amplifier SA are P1 and P2.
Data is written in the bit line BL in the order of the memory cells C0n and C1n.

FIG. 9 is a waveform diagram of a write operation to the memory cells C2n and C3n when the word line WL2 is selected in the same dynamic semiconductor memory device. Similar to the case of FIG. 8, the connection gates of the bit line BL and the sense amplifier SA are selected in the order of P1 and P2, and the data is written in the order of the memory C3n and then the memory C3n.

Here, the word line WL2 is selected in FIG.
In the case of, the data is first written into the memory cell C2n, and then the bit line B to which this memory cell C2n is connected.
A memory cell C3n in which BL1n and BL3n arranged so as to sandwich L2n form a bit line pair and are connected to the bit line B3n
Write to. The potential amplitudes of the bit lines BL1n and BL3n are from the precharge potential Vcc / 2 to 0V and Vcc with respect to the memory cell, the signs are different and the absolute values are equal to Vcc / 2. Therefore, sandwiched between these,
The noise due to the capacitive coupling between the bit lines, which is received by the bit line BL2n which is separated from the sense amplifier and is electrically floating, is canceled out by plus or minus and becomes equal. Therefore, in this case, in writing to the memory cells C2n and C3n, noise due to capacitive coupling between the bit lines is canceled.

However, the word line WL1 is selected in FIG.
In the case of, the memory cell C0n connected to the bit line BL0n is first written, and the gate control signal P0
1 is inactivated, and the bit line BL0n becomes electrically floating. Here, when the bit line BL1n connected to the memory cell C1n to which writing is performed after P2 is activated and its complementary bit line BL3n are amplitude-amplified by the sense amplifier SA, the bit line BL0n causes a capacitance between the bit lines. Receive noise due to coupling. Assuming that the bit line capacitance is CB and the coupling capacitance between the bit lines is CBB, the magnitude is 2 × (Vcc / 2) × CBB / CB because in the worst case, the potential amplitude noise of the bit lines on both sides is received. Become.

Therefore, in the worst case, the written data is relatively damaged by 2CBB / CB, so that the signal amount at the time of reading is also reduced accordingly. Such a decrease in the signal amount at the time of reading data becomes a factor of lowering the operation margin of the sense amplifier. It should be noted that this write noise is not due to the method in which the sense amplifier SA is not shared by a plurality of bit lines BL and all bit line pairs are activated at the same time.

In FIG. 10, a NAND type cell in which a plurality of DRAM cells are connected in series is used as a basic unit, and the word line closest to the bit line contact is separated to select the bit line to which the data is transferred and the return is performed. 2 is an example of a NAND type DRAM that realizes a type bit line configuration. Also in this case, the problem of data writing noise is the same as in the example of FIG.

[0011]

As described above, conventionally, when a plurality of bit line pairs share a smaller number of sense amplifiers, write data receives noise due to capacitive coupling between bit lines. This has been a factor that reduces the operation margin of the sense amplifier.

The present invention has been made in consideration of the above circumstances, and an object thereof is to reduce noise at the time of writing due to capacitive coupling between bit lines, and to sense amplifier at the time of reading. It is an object of the present invention to provide a semiconductor memory device capable of increasing the operation margin.

[0013]

In order to solve the above problems, the present invention employs the following configurations.

That is, according to the present invention, a plurality of bit line pairs share a smaller number of sense amplifiers, and the precharge potential of the bit line is between the "H" and "L" write potentials for the memory cell. In a semiconductor memory device that sequentially reads or writes data in memory cells at different times, among memory cells selected by the same word line, a bit line to which a memory cell to which data has been written first is connected is A circuit for controlling the activation order of the bit lines is provided so that a bit line pair to be written later is arranged so as to be sandwiched between them.

The preferred embodiments of the present invention are as follows. (1) Each bit line pair has a memory cell arranged at either one of two intersections with the same word line, and the bit line pair activated first with respect to the same word line is activated later. Memory cells are placed on the bit line side that is sandwiched between the pair of bit lines. (2) It is a folded bit line method in which one sense amplifier is shared by four bit lines, and two of them are paired bit lines. Which of the bit line pairs is connected to the cell to be written? Switching the activation order of bit line pairs by.

[0016]

According to the present invention, among the memory cells selected by the same word line, the bit line to which the memory cell to which data has been written first is connected is adjacent to the bit line pair to which data is to be written later. By controlling the activation order of the bit lines so that the bit lines are arranged so as to be sandwiched, noise received from the bit line connected to the memory cell previously written by the bit line pair to be written later is canceled. Therefore, when a plurality of bit line pairs share a smaller number of sense amplifiers, write data noise due to capacitive coupling between bit lines can be eliminated or significantly reduced. It is possible to secure a sufficient operating margin.

[0017]

The details of the present invention will be described below with reference to the illustrated embodiments.

FIG. 1 is a circuit configuration diagram showing a semiconductor memory device according to the first embodiment of the present invention. In this embodiment,
The four bit lines BL (BL0n, BL1n, BL2n, BL3n) connected to one sense amplifier SA (more specifically, sense amplifier / equalize circuit, I / O, etc.) are
Gates controlled by the control signals P1 and P2 are arranged so that L0n and BL2n and BL1n and BL3n form a bit line pair. In this example, the order of connection of the memory cells C to these gates and word lines WL is periodic for each sense amplifier, that is, for every four bit lines.

At the intersection of the word line WL and the bit line BL,
The memory cell C is arranged on one of the two bit lines forming a pair. The memory cell C is a DRAM cell composed of 1 transistor / 1 capacitor.

FIG. 2 is a first operation waveform diagram of this embodiment.
This shows the write operation to the memory cell when the word line WL1 in FIG. 1 is selected. FIG. 3 is a second operation waveform diagram of the present embodiment, which is a write operation when the word line WL2 of FIG. 1 is selected. In this embodiment, when the word line WL1 is selected, the memory cells C0n and C1n are written, and when the word line WL2 is selected, the memory cells C2n and C3n are written. In addition, in this embodiment, the bit line B depends on the selected word line WL.
Control signal P1 of gate connecting L and sense amplifier SA
And the order of activation of P2 is different.

First, the operation waveform diagram of FIG. 2 will be described. Before writing to the memory cell C, all the bit lines BL are precharged to the exact middle of the write potential of "1" and the write potential of "0" to the memory cell C. The memory cell C1n is connected to the bit line BL1n, and BL1n is a pair of bit lines BL0n and B0n.
It is sandwiched between L2n. Therefore, according to the rules of the claims, first, the control signal P2 is selected to write to the memory cell C1n to activate the bit line pair of BL1n and BL3n. After that, P2 is deselected and the bit line B
L1n and BL3n are brought into an electrically floating state. Furthermore, P
B to select 1 and write to memory cell C0n
Activates the bit line pair of L0n and BL2n to activate the word line WL.
Hold 1 to lock the data in the memory cell.

By the activation of the sense amplifier for the second time, BL0n and BL2n, which are two adjacent bit lines of BL1n to which data is previously written, have a write potential "1" for the memory cell rather than the precharge potential. And “0”
Of the bit line BL sandwiched between them.
The capacitive coupling noise received by 1n is just canceled because the positive and negative potential amplitude widths are the same. Therefore, both the previously written data of the memory cell C1n and the later written data of the memory cell C0n can be written in the memory cell without receiving capacitive coupling noise with respect to the data write potential.

In the operation of FIG. 3, the word line WL2 is selected and writing is performed in the memory cells C2n and C3n. In this case, the bit line BL2n connected to the memory cell C2n is sandwiched between the bit line pair BL1n and BL3n. Therefore, since the memory cell C2n is written first and the memory cell C3n is written later, the activation order of P1 and P2 is different from the case of FIG. Then, according to the completely same principle, the memory cell C2n
And the write potential for C3n is not subject to capacitive coupling noise.

If the precharge potential of the bit line BL is exactly in the middle of the two write potentials of "0" and "1" for the memory cell C, the bit line in the write to the memory cell C according to the principle described here. Capacitively coupled noise between can be completely eliminated. Further, the potential amplitude of the bit line BL driven across the bit line BL in which the data is previously written has a sign as long as the precharge potential of the bit line BL is between two types of write potentials to the memory cell C. The opposite is true, and therefore, the capacitive coupling noises received by the bit line BL to which data has been previously written are canceled by these potential amplitudes.

Therefore, in the worst case, noise is clearly reduced as compared with the conventional case in which the signs of the potential amplitudes of the adjacent bit lines are the same, so the precharge potential of the bit line BL must be strictly in the middle. Even if it deviates from this value, the effect of noise reduction intended by the present invention appears.

FIG. 4 is a circuit configuration diagram showing a semiconductor memory device according to the second embodiment of the present invention. In this example, the arrangement of the memory cells C along the word line WL and the arrangement of the connection gates of the bit lines BL and the sense amplifiers SA are periodically arranged for every eight bit lines, that is, for every two sense amplifiers.

The operation principle and operation waveform are exactly the same as those in the first embodiment, but in this embodiment, the bit line capacitive coupling noise at the time of reading data can be reduced to half that in the conventional case.

FIG. 5 is a circuit configuration diagram showing a semiconductor memory device according to the third embodiment of the present invention. In this embodiment, a NAND type cell in which a plurality of DRAM cells are connected in series is used as a basic unit, and a word line WL closest to a bit line contact is separated to transfer data between a memory cell C and a bit line BL. And the folded bit line configuration is realized. Also, one sense amplifier SA is shared by four bit lines BL, and two gate lines driven by the control signals P1 and P2 so that two bit lines BL form a bit line pair and are connected to the sense amplifier SA. Are arranged.

In this embodiment, the order of reading is the cell numbers in the figure: (1) (2) (3) (4) (5) (6) (7) (8)
(And (1) '(2)' (3) '(4)' (5) '(6)' (7) '(8)), but the order of writing is exactly the opposite. Not
(7) (8) (6) (5) (3) (4) (2) (1) (and (7) '(8)' (6) '(5)' (3)
The order is' (4) '(2)' (1)). FIG. 6 is an example of operation waveforms in this embodiment. Also in this case, similar to the first embodiment, it is possible to reduce the noise of the write data due to the capacitive coupling between the bit lines.

The present invention is not limited to the above embodiments. In the embodiment, the example of the dynamic semiconductor memory device has been described, but the invention can be applied to a nonvolatile semiconductor memory device as long as a plurality of bit line pairs share a smaller number of sense amplifiers. In addition, various modifications can be made without departing from the scope of the present invention.

[0031]

As described in detail above, according to the present invention, in a configuration in which a plurality of bit line pairs share a smaller number of sense amplifiers, the activation order of the bit line pairs is devised, When sharing a smaller number of sense amplifiers with multiple bit line pairs, write data noise due to capacitive coupling between bit lines can be eliminated or greatly reduced, and the sense amplifier operating margin at the time of reading is secured. The semiconductor memory device can be realized.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing a semiconductor memory device according to a first embodiment.

FIG. 2 is a first operation waveform diagram in the first embodiment.

FIG. 3 is a second operation waveform diagram in the first embodiment.

FIG. 4 is a circuit configuration diagram showing a semiconductor memory device according to a second embodiment.

FIG. 5 is a circuit configuration diagram showing a semiconductor memory device according to a third embodiment.

FIG. 6 is an operation waveform diagram in the third embodiment.

FIG. 7 is a circuit configuration diagram showing a conventional semiconductor memory device having a folded bit line configuration.

FIG. 8 is a first operation waveform diagram in the conventional device.

FIG. 9 is a second operation waveform diagram in the conventional device.

FIG. 10 is a circuit configuration diagram showing an example of a conventional NAND DRAM.

[Explanation of symbols]

 BL ... bit line WL ... word line C ... memory cell SA ... sense amplifier P ... control signal

Claims (2)

[Claims] 1. A plurality of bit line pairs share a smaller number of sense amplifiers, and the precharge potential of the bit lines is set to a potential between "H" and "L" write potentials for a memory cell, and sense is performed. In a semiconductor memory device that sequentially reads and writes data in a memory cell by sequentially switching bit line pairs connected to an amplifier, among memory cells selected by the same word line,
A means for controlling the activation order of the bit line pair is provided so that the bit line to which the memory cell to which the writing is performed is connected is sandwiched by the bit line pair to be written later. A semiconductor memory device characterized by the above. 2. A plurality of bit line pairs share a smaller number of sense amplifiers, and the precharge potential of the bit lines is set to a potential between "H" and "L" write potentials for the memory cell, and sense is performed. In a semiconductor memory device that sequentially reads and writes data in a memory cell by sequentially switching bit line pairs connected to an amplifier, each bit line pair has a memory cell arranged at either one of two intersections with the same word line. The semiconductor memory device is characterized in that, for the same word line, a memory cell is arranged on a bit line side which is sandwiched between bit line pairs which are activated first and bit lines which are activated later.