SU397965A1 - - Google Patents

Description

one

This invention relates to computing and automation devices.

Memory devices for storing multilevel information are known, containing memory elements stitched with a branched numeric bus, control bit keys, the first inputs of which are connected to the polling clock, and the second to the write data buses, the selective polling core and the selective recording heart, the various branches of the number; the howl of the UNI, and the playback amplifiers connected to the output bus passed through the memory cores.

The aim of the invention is to simplify the device.

The proposed device is distinguished by the fact that it contains the front-read control bits that are stitched through the selective interrogation cores in accordance with the numerical width and through the selective cores of the intersection counter with the numerical thickness.

This simplifies the device.

The drawing shows a schematic electrical circuit diagram.

The device contains write code buses 1 for supplying the recorded information, storing the heart 2 for storing information, control bit switches 3 for generating control pulses for 2

writing and reading, a write-read control bit 4 for transmitting control pulses, selective interrogation cores 5, upper branch 6 of the number field, selective write cores 7, lower branch 8 of the number field, numerical write-read bar 9 for recording and reading information, polling clock 10 for supplying control signals to the control bit switches, device output buses 1J, and playback amplifiers 12.

The device works as follows. To write code information

Record 1 is applied to a series of pulses. The number of pulses in a series corresponds to the number of discrete levels to which the memory core 2 should be re-magnetized. These pulses periodically open the control bit switches 3. Positive-polarity pulses are sent to the selected write-read control 4 bits. After the passage of the first impulse, the band-m 4 selector cores 5 of the upper branches 6 re-magnetize into the state,., And the cores 7 of the sawed branches 8 - into the state -Br. In the time interval between the first and second pulses, a current pulse is applied to the storage element along branches 6 and 8 on the selected read write-number bus 9, branching 5 and 7 into the -jS state, since since when the first impulse is fed through the bus 4 in the III-B state, the core 7 appears, then under the action of the impulse passing through the spike 9, it begins to peep: this leads to the - {- B, - signal, increasing the efficiency of the branch 8. This causes to an increase in the numerical current in branch 6 (the card 5 does not reversal), and with edovatelno to the predominance amlervitkov memory core 6, under the action of which the core 2 is remagnetized by one step. The switching floors are chosen such that the core 2 is moved only by passing a numerical current. In the memory element, where the current pulse across the bus 4 was missing, the core 7 is in the -f-Sr state, and the core 5 is in the + Br-il-Br state, which is equivalent to the neutral or neutral state of the memory element (write there is no or confirmation of zero information). After the first step of information has been recorded, the next positive impulse enters the memory core 2 through the spike 4, which again brings the core 7 to the -BG state, and in the core 5 it confirms the +3, condition. A second pulse follows the second bus 4 an impulse on a numeric bus I that records the second step of information in core 2, etc. Thus, in accordance with the number of pulses fed on a particular bus 4, corresponding information states are set in the memory cores 2. After the last pulse is applied over a busbar 4, a numerical pulse records the last step of information into the element, after which, regardless of the number of pulses on bus 9, the state is established and saved in the element when cores 5 and 7 are in the + 8 position. The numerical current can be chosen large enough for fast switching of the selection cores, i.e. for high speed and for a clear distinction of information steps. The imbalance current of branches 6, 8 should create a field greater than the field of core trog 2. At the end of the recording, a polling pulse is generated on the clock bus of the olros 10, which opens the keys of all 3 bits, and the buses 4 are given negative pulses that set the cores position -In; and the cores 7 are in the position + B, -, which corresponds to the polling initial state of the elements. At the end of the polling measure, the following number can be selected: the moving number, and a similar recording is made to it. If it is required to interrogate any number, then an impulse current is supplied over the corresponding bus 9, which, by switching the core 5 from state -5,. in state + Br, writes off the information step from core 2, and in output bus I, output signal is sent that goes to playback amplifier 12. Then the next onros pulse is fed, which returns the cores 5 to the initial state, followed by the next numeric pulses as many times as many ion levels are taken. The last thing in reading the information is the impul: s, which establishes the definition: the axial state, i.e. the pulse count 4 of the negative zero, in the input elements. After reading the information from the selected number, another number can be queried or written to the previously defined numbers. Thus, interrogation and search for information occur arbitrarily according to commands from the control device. The device allows the operation to add numbers at any time, i.e., any number can be written to the number previously recorded. The process of writing and reading information is quite simple, the number of control elements is small and their functional purpose is simple. The control pulses and their duration, depending on the operating conditions, can be chosen differently in a wide range. The device does not contain elements with a complex magnetic conductor, the magnetic parameters of which are worse than those of the cores, the dimensions are larger, and the firmware is more complicated. The subject matter of the invention is a MEMORY device containing memory elements stitched with a ramified numeric bus, control bit keys, the first inputs of which are connected to the polling clock bus, and the second are coded write buses, a selective polling center, and a selective reference core which are passed through different numeric branches. , and playback amplifiers, connected to the output bus, missed through memory cores, are different in that, in order to simplify the device and increase its speed, it is overclocked; The data points for the control of the read-out, stitched through the selective interrogators, are in accordance with the Numeric Shiia and through the selective write cores stretch with the numeric bus.

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