SU402063A1 - MEMORIZING DEVICE WITH TWO MEMORABLE ELEMENTS ON A DISCHARGE - Google Patents

Description

one

The proposed bit line connection unit can be used in a memory unit with two memory elements per information bit, in which bit lines are used simultaneously to record and retrieve information.

To reduce the noise arising at the input of the playback amplifier from the recording current, in the known memory, the bit lines are switched on by a bridge circuit. In this case, the write driver is connected to the diagonal of the bridge, and the playback amplifier is connected to the bit lines via a transformer. On the far side of the bit lines, terminating resistances are usually included.

A disadvantage of the known circuits is that when the parameters of real bit lines are scattered, the unbalance of the bridge occurs, and the input from the recording current pulses interferes with the input of the amplifier, which leads to a decrease in the speed of the charger.

The purpose of the invention is to reduce the noise from the recording current, resulting from the variation in the parameters of the bit lines, and to increase the speed of the recording device.

This goal is achieved by the fact that, in order to improve noise immunity and speed, the beginning of the first winding and the end of the second winding of the input transformer are connected to the outputs of one of the matching resistances of the first discharge line through a notch. The end of the first winding and the beginning of the second winding of the input transformer are connected to the outputs of one of the matching resistances of the second discharge line.

The circuit for switching on spurious memory lines is shown in the drawing.

Bit lines 1 of the memory unit with two storage elements 2 per bit of information and matching resistances 3 and 4 are connected in a bridge circuit. Record shaper 5 is included in the bridge diagonal. Matching resistance 3 consists of two

series-connected resistances 6 and 7, and matching resistance 4 - of two series-connected. x. resistances 8 and 9. Some opposite ends of the two primary windings 10 and I of the input transformer 12 of the playback amplifier 13 are connected to the resistance 7 via the relay sector 14, and the other opposite ends are connected directly to the resistance 9. The numerical line 15 serves to supply the address reading current .

With the flow of discharge current recording due to the artificial unbalance of the bridge circuit, achieved by dividing the terminating resistances 3 and 4 into its component parts 6, 7

and 8, 9 at the ends of the chains of the primary windings 10

and 11 transformer 12 is provided with a potential difference of the same sign. In this case, the rejector 14 for the currents flowing through its windings represents a high resistance and reduces the noise at the input of the amplifier 13. The magnitude of the components 6 and 8 of the matching resistances 3 and 4 is selected based on the maximum variation of the parameters of the discharge lines 1. In addition, e. DS from the currents weakened by the injector are mutually subtracted in the transformer (12). When reading for the currents of the useful signals, the windings of the chopper 14 are switched in opposite, and the primary windings are in accordance with.

With this bit line connection, the chopper has practically no resistance for the useful signals, which are summed in the transformer (12).

Thus, the proposed scheme makes it possible to reduce the level of interference caused by the spread of the parameters of the bit lines without attenuating the useful signal and, consequently, to increase the memory speed.

An experimental study of the proposed bridge circuit for connecting discharge lines as part of a high-speed memory device on a CEM cylindrical magnetic film showed its high efficiency.

Subject invention

A storage device with two storage elements per discharge, containing in each discharge bit drivers, a floor, connected to two discharge buses interconnected through successively connected matching resistors, a read amplifier with a transformer input and a rejector, characterized in that in order to increase the noise immunity and speed of the device, the beginning of the first winding and the end of the second winding of the input transformer of the amplifier are connected to the outputs of one of the terminating resistors via a chopper in the first pair of bit buses, and the end of the first winding and the start of the second winding of the input transformer of the amplifier are connected to the outputs of one of the matching resistors of the second pair of bit buses.