SU514294A1 - Fault Detection Device - Google Patents

Description

The known device has no connection between the outputs of the single-ended delay elements and the inputs of the decoders of a single fault and operability. With a small test length, this may lead to an additional decrease in the reliability of the checks.

The aim of the invention is to increase the reliability of the device. In the described device this is achieved by the fact that, in the letters, the inputs of the adder are connected to the corresponding outputs of the tested block, the outputs to the corresponding inputs of the decoders of a single fault and operability. This allows you to register the distortion of the output codes of the block under test, the accumulating adder registering the sum of parallel codes (rows), and the adder and shift register - the sum of successive codes (columns) independent of the length of the accumulating adder, and the decoders are one OCH error and health conditions take into account the information stored in the elements of a single delay adder.

The drawing shows a diagram of the described device.

The test generator 1 is connected by its outputs to the tested block 2 and to the decoder 3 of the end of the test. The tested block 2 is connected with all its outputs to the inputs of the accumulating adder 4 of the parallel type and to the inputs of the adder 5 containing the cascades of combinational adders 6i-63, and the outputs of the sum of the combinational adders of the previous cascades are connected to the inputs of the combinational adders in the subsequent cascades, and the outputs of the carries combinational adders 6i-63 through the delay elements 7i-7z are connected to the inputs of the same adders 6i-63. The output of the adder 5 is connected to the input of the lower bit of the shift register 8. The input block 9 rearranges the test generator 1, the decoder 10 single faults and the decoder. And the health conditions are configured to check the blocks of a certain type. The output of the health decoder is connected to the indicator 12. The pulse shaper 13 contains a trigger 14, an AND 15 element and a multivibrator 16. The shaper 13 starts up via control input 17. The output 18 of pulse signals is connected to the first inputs of test generator 1 of the tested unit 2 accumulating adder 4, register 8 shift, elements 7i-7z delay. The installation input 19 performs the initial installation of all device nodes.

When a signal arrives at input 19 of the set. KI, the initial installation of all the nodes of the device with memory elements (for example, triggers) is made. When a signal arrives at control input 17 of the former 13, trigger 14 is moved to the state "1, while the element "And 15, and the clock pulses from the output of the multivibrator 16 through the element" And 15 arrive

at the output 18 of the pulse generator 13, the test generator 1 begins to output to all its outputs the pulse sequences checking block 2. The output codes of the tested block 2 are summed and stored in the accumulator 4 of the parallel type, and the successive codes of the outputs of the tested block 2 summed in the cascades of combinational adders 6i-63 and fed to the input of the shift register 8, while the sequential summation transfers are performed using the 7i-7z elements of a single-cycle delay. The process of test generation and operation of the entire device continues until the generation of test results of the generator 1 tests, indicating the end of the test cycle. In this case, the decoder 3 is triggered, the signal that appears at its output sets the trigger 14

in the "zero state, the element" AND 15 is closed and the arrival of the clock pulses from the output 18 is terminated.

The totalizer of the output codes (rows) of the block 2 to be checked is stored in the accumulator 4, the total of the consecutive codes (columns) is stored in register 8, and the adduct delay elements contain "overflow units of the sum of the columns." These sums and overflows determine the state of the checked block 2. The decoder 11 health and the indicator 12 operate with the true value of the sums and overflows, and the decoder 10 single faults recodes the sums and overflows (in case of their distortions) in the position of pegs.

The invention may be illustrated by a simple example. We assume that the tested block has two outputs “a and“ b. Table 1 lists the approximate output codes and the overflow of the operable unit to be tested, and also shows the states of the accumulating adder, element of the delayed delay, and the generator of the shift in case of registration with adder 5 and register 8 of the transfer from the highest bit of the accumulating adder so that manufactured in a known device. Table 2 gives the code distortion on the output “a, caused by some kind of malfunction. how

can be seen from the table. 2, this does not lead to any change of codes in the registration nodes. Table 3 shows the states of the adder, a single-ended delay element and the shift register in case an additional adder is connected to the outputs of the tested block, provided that there is no distortion in the tested block, and in Table 4 — or there is a distortion of the similar table. 2. As can be seen from the table. 3 and 4 at the end of the test cycle is changed, compared to the true one, only the state of the shift register, so in this case only the shift register connected via an additional adder directly to the outputs of the tested block is able to detect faults.

Table I

Claims (1)

G formula of the invention Fault finding device containing pulse driver, test generator, input unit, test end decoders, single faults and operability, shift register, adder, indicator and parallel accumulator, discharge outputs which are connected to the corresponding inputs of single-source non-right decoders and health, the inputs are connected to the corresponding outputs of the tested block, the input of which is connected to the generator output test, the output of the test generator through the decoder end of the test is connected to the input of the pulse shaper, the control input of which is connected to the input of the device, the output of the input block is connected to the inputs of the test generator, the single-fault decoder and the health decoder, the output of which is connected to the indicator input, the output of the pulse generator, are connected to the corresponding inputs of the test generator, the accumulator of the parallel type, the tested block, the adder and the shift register, the input of the lower shift register is connected with the output of the adder, the outputs of the register bits the shear is connected to the corresponding inputs of single-fault and health decoders, the control inputs of the test generator, the test block, the accumulating parallel-type adder, the adder and the register are connected to the device input, characterized in that, in order to increase the reliability of the device, the inputs of the adder connected to the corresponding outputs of the tested block, the outputs to the corresponding inputs of the decoders of single faults and operability.