SU478309A1 - Fault Detection Device - Google Patents

Description

(54) TROUBLESHOOTING DEVICE

The invention relates to the field of computing and can be used to automatically check and troubleshoot computers. Devices are known for detecting faults in digital computer units containing a pulse driver, test generator, descramblers, node, input, health indicator, accumulating torus sum, whose bit outputs are connected to the test results analysis unit. The advantage of such devices is that they do not require the creation of a generator of reference signals and simplify the registration of the output codes of the block being tested and the resolution of faults in it. However, in such devices, the accumulating parallel-type adder detects only those faults that lead to a change in the number of units in the output pulse sequences (columns) of the tested block. In the meantime, there are faults that change only the timing diagram of the location of units in the columns, and the number of units remain unchanged:. The purpose of the invention is to increase the reliability of the test results. To do this, an additional adder and a shift register are entered into the device, with the carry outputs from the higher bits of accumulating adders via the ADD; the target adder is connected to the shift register input, and the shift register outputs are connected to the health decryptor and the single faults decryptor. This allows you to register distortions of the output codes of the block being tested, and accumulating adders register the truth of the columns by the number of units of them, and the additional adder and shift register check the running codes both by the number of units in the translations from the leading bits diagrams of the location of units in the translations. With an increase in the number of accumulating adders (with a decrease in the size of each), the efficiency of checks increases. FIG. 1 shows a diagram of the device; la fig. 2 is an example for explaining its operation. The test generator 1 is connected by its outputs to the tested unit 2 and to the decoder 3 of the test termination. The tested block 2 is connected with all its outputs to parallel accumulating accumulators, and the bits of accumulating accumulators are connected to the decoder 5 of single faults and in parallel to the decay of the serviceability indicator 6, which is connected to the indicator 7. the higher bits of the accumulating adders are connected via single-digit adders 9–9 to –13 successively connected to the input of the register 10 of the shift. One-digit adders 9-9 contain combinational totalizers, 1 3 single- and clock delay elements, which are connected by their inputs to the outputs of the transfers of combinational adders, and the outputs are connected to the inputs of the same combinational cy.iAMaTopOB. The outputs of the adders 11 are connected to the inputs of the subsequent single-digit adders 9. The multivibrator 13 is connected via button 14 to the bus 15 of the installation and to BeHTHJno 16, which is connected by its other input to the single output of the trigger 17. The valve 16 is connected to the input of the amplifier 18, the output 19 of which is connected to device nodes. The trigger 17 is set to 1 via the trigger input 20. The decoders 5 and 6, as well as the test generator 1, are rebuilt to check blocks of a certain type using the input block 21; 22 and 23, respectively, a pulse shaper and an additional adder, made on the basis of adders 9; 24 - single-fault decoder outputs; 25-28 outputs of the tested block. The device works as follows. When the button 14 is pressed, the inputs 15 of the installation receive 1 pulses that set all the nodes of the device and the tested block 2 into the initial state. When the start signal arrives at the input 20, the trigger 17 is set to one, the trigger 17 opens the valve 16, and The clock pulses from the output of the multivibrator 13 through the valve 16 and the amplifier 18 are fed to the bus 19. The test generator I begins to output pulse sequences through all of its outputs that check block 2. The output codes of the tested block 2 are summed and stored It is in the accumulator 4 parallel type, and successive transfers codes from MSB adders 4, bitwise summing Referring in cascades odnorazr 1dnyh $ 9 serial adders action, are input to the shift register 10. In this case, sequential summation transfers are performed using single-ended delay elements 12. The process of test generation and operation of the entire device continues until the generation of test results of the generator 1 tests, indicating the end of the test cycle. In this case, the decoder 3 is triggered, and the signal appearing at its output sets the trigger 17 to 0, the valve 16 closes and the flow of clock pulses from the output 19 of the amplifier 18 is stopped. In the accumulating adders the total sums of the output codes of the tested block 2 will be stored, and the register 1O will set the state corresponding to the sum of the carry codes from the higher bits of the adders 4. These sums determine the state of the tested block 2. Deshi (} and the indicator 7 is triggered with the true value of the sums, and the decoder 5 single faults recodes the sums (in case of their distortions) in the position of faulty elements. The essence of the invention can be explained with a simple example. There are 25-28 output circuits, which are connected to the inputs of accumulating adders 4. Table 1 shows the approximate output codes of the operable unit under test, and also shows the states of accumulating adders on each test cycle cycle. The same table shows (the senior house down) consecutive carry codes: co. high bit of the first accumulating adder (OOU) and from the high bit of the second accumulating adder (010b). In the shift register, at the end of the verification cycle, the sum of the carry codes (ITO) is set, and the accumulating adders - the total values of 10 and O1. These amounts are deciphered as intact.

We believe that some kind of malfunction distorts the time diagram of the location of units at outputs 25 and 27, but leaves the number of units at each output unchanged. In tab. 2 shows these distortions. It follows that the device for detecting faults, containing a pulse shaper, a test generator, an input unit, decoders for the end of testing single faults and operability, an indicator and accumulative adders, whose discharge outputs are connected to the corresponding decoder inputs single faults and health, inputs

Table 1.

Only the state of the shift register (1OOO) is changed in comparison with the true test cycle, so in this case only the shift register is able to diagnose faults.

Table 2. are connected to the corresponding outputs of the tested block, the input of which is connected to the output of the test generator, the output of the test generator through deshi (} the test end generator is connected to the input of the pulse generator, the control input of which is connected to the input of the device, the output of the input block is connected to the inputs of the test generator, the distance (| a single fault malfunction and a decoder

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health, the output of which is connected to the input of the indicator, the outputs of the driver of the impulse signals are connected to the corresponding inputs of the test generator, accumulating adders and the tested block, the outputs of the decoder of the SINGLE faults are connected to the corresponding outputs of the device by the fact that, in order to increase the reliability of the results of the test, a supplementary additional adder and

shift offset, and the carry outputs from the upper bits of accumulating adders through an additional adder are connected to the first input of the shift register, the second p of the third inputs of which are connected to the corresponding outputs of the pulse generator, the outputs of the shift register bits are connected to the corresponding inputs of the health decoder and the single fault decoder .