SU1049913A1 - Device for checking logic unit - Google Patents

Abstract

A DEVICE FOR THE CONTROL OF LOGICAL BLOCKS, containing a clock counter, adder-subtractor, display unit, the output of the adder-subtractor is connected to the information input of the display unit, characterized by the fact that, in order to reduce the control time of the same logical group, JB it entered a register, sum Matrix modulo two, trigger, two ele7 "nta, And, a group of elements And, a group of combinational adders, a generator of clock pulses, the output of the generator of clock pulses connected to the first input of the first element And, the output of which is connected to the clock input of the adder-subtractor and the input of the counter of clock pulses, the inputs of which are connected to the inputs of controlled logical blocks and the inputs of the second element And and the first inputs of the corresponding elements And groups, the second inputs of which are connected to the corresponding outputs of the register, the outputs of the elements And the groups are connected to the inputs of the modulo two adder, the output of the second element I is connected to the zero input of the trigger, the single input of which is the trigger input of the device, zero i and trigger unit outputs connected respectively to the control vho-. (The house of the display unit and the second input of the first element I, the information inputs of the adder-subtractor are connected to the outputs of combinational adders of the group, the inputs of which are connected to the corresponding outputs of the monitored logic blocks, the output of the modulo-two adder is connected to the input .1 from the sum (difference) of the adder - read: l ... V DO

Description

} The invention relates to computing and can be used to control logic circuits during testing. Tests can be carried out by the method of single sampling, when from a batch of similar logic circuits, K logical circuits are tested; In this case, if at least one of the K logic samples failed, then all the batch of circuits is rejected. In case all the K logic circuits in the performance sample are received, the batch accepts p. A device for monitoring logic blocks is known, comprising a multi-plexor, a control unit, a storage unit for reference output sets, a storage unit for reference input selections, and a drift adder — l. However, in this device, the monitoring time depends on the number of outputs of the monitored unit. The closest technical solution to the invention is a logic control device comprising a Walsh function generator, a switch, a clock counter, an algebraic adder, a counting direction setting unit and a display unit, the outputs of the Walsh function generator being connected to the corresponding inputs of the logic being monitored and switch, the output of which is connected to the input of the unit for determining the direction of the budget, the outputs of which are connected to the control inputs of the algebraic adder, inf rmatsionnye whose inputs are connected to outputs controlled by the logic circuit, the output of the counter clock soybeans. It is connected to the clock input of an algebraic adder, the outputs of which are connected to the input of the display unit z. However, in this device, the outputs of one controlled circuit are connected to the information inputs of the algebraic adder, which causes an increase in the control group of logic circuits compared to the control time of one logical scheme. The purpose of the invention is to reduce the time control of a group of similar logical blocks. The goal is achieved by the fact that the device for control logic blocks, containing a clock counter, adder-subtractor, display unit, the output of the adder-subtractor is connected to the information input of the display unit, a register is entered, a modulator adder two, a trigger, two elements And , a group of elements And, a group of combinational adders, a generator of clock pulses, and the output of the generator of clock pulses is connected to the first input of the initial element of And, the output of which is connected to the clock input of the adder-you The tattel and the clock counter input, the outputs of which are connected to the inputs of monitored logic blocks and the inputs of the second; element.And AND and the first inputs of the corresponding elements AND groups, the second inputs of which are connected to the corresponding outputs of the register, the outputs of the elements AND group are connected to the inputs of modulators two, the output of the second element I is connected to the zero input of the trigger, the single input of which is the start input of the device, the zero and single outputs of the trigger are connected respectively to the control the main input of the display unit and the second input of the first element I, the information inputs of the adder-subtractor are connected to the outputs of the combinational adders. groups whose inputs are connected to the corresponding outputs of the controlled logical blocks, the output of the modulo-two adder is connected to the input of the sum (difference) of the adder subtractor, The drawing shows a block diagram of a device for monitoring logical blocks. The device contains a generator of 1 clock pulses, the first 2 and second 3 elements And, the counter k clock, pulse, pulse group induction adders 5, adder-subtractor 6, trigger 7, register 8, group of elements AND 9, adder 10 modulo two, display unit 11, triggering device input 12, group of controlled logical blocks 13., The output of the T clock pulse generator is connected to the first the input of the first element I2; The output of the first element I2 is connected to the input of the counter of 4-stroke pulses and the clock input of the Algebraic adder 6. You move the counter of 4 clock pulses connected to the inputs of the second element IZ, control1; 1 logic blocks IZ and the first inputs u9 elements and group 8 register outputs are connected to second inputs of respective elements u9 group. The outputs of the I9 elements of the group are connected to the inputs of the adder 10 modulo two, the output of which is connected to the input of the sum (difference) of the adder of the subtractor 6, The outputs of the adder-calculator of the 6 are connected to the information inputs of the display unit 11, . The number of combinations (total l adders 5 of the group is equal to the number of outputs of controlled logical blocks 13, and the first outputs of all controlled logical blocks 13 are connected to the inputs of the first combiner 5, all second outputs of controlled logical blocks 13 are connected to the inputs of the second combiner 5, etc. .. The output of the second IZ element is connected to the zero input of the trigger 7. The outputs of the trigger 7 are connected to the second input of the first element I2 and to the control input of the indication unit 11. Single output of the trigger. , Is the triggering input of the device 12. The device operates as follows: After the power supply, the device is reset: trigger 7 and counter k is set to zero, the constant is written to register 8 in reference subtractor 6 the result of the control with the opposite sign. (The circuit for setting the device to the initial state is not shown in the drawing.) A start pulse is applied to the input 12 of the device, which sets trigger 7 into one state. In this case, a single signal from a single output of the trigger 7 is fed to the second input of the element I2 and permit. the receipt of pulses from the generator 1 output to the counting vhrd of counter i and to the clock input of the total; 6, From the output of the counter M to the inputs of the monitored units 13, combinations of input signals begin to flow. The same signals simultaneously arrive at the first inputs of elements 134 I9 of the group and to the inputs of the element IZ. The second inputs of the elements from the group receive signals stored in register 8. The outputs of elements I9 receive signals that arrive at the outputs of the adder 10. From the output of the adder 10, the control input of the adder-subtractor 6 receives the signal adder-subtractor 6 operating mode - addition or subtraction, “Signals from the outputs of monitored units 13 are fed to the inputs of adders 5 of the group. In this case, the inputs from the first outputs of the monitored units 13 to the inputs of the second adder 5 grams ppy receives signals from the second outputs of the units 13, etc. Each adder of group 5 produces the addition of binary signals. The signals from the outputs of the adders of the 5 group to the post; they go to the information inputs of the adder 6. The adder 6, by the signal fed to its control input from the output of the adder 10 modulo two, adds the values of the signals that went to its information inputs to the previous action ( its control input is given a signal or subtraction of the values of the signals received at its information inputs from the result of the previous action (if signal 1 is given at its control input), synchronization of the operation of the adder 6 is performed actual pulses arriving at its clock input from the output of element I2, "After the counter of the last signal combination (lt1ooo, 1) arrives at the output of the counter, a single signal appears at the output of the FROM element, which sets trigger 7 to the zero state. the zero signal from the single output of the trigger 7, coming to the second input of the element I2, prohibits the passage of clock pulses from the output of the generator 1 to the counting input of the counter k and the clock stroke of the adder 6 "At the same time, the single signal from the zero output of the trigger 7 goes to control yuschy input unit 1 and the display razreliiaeT result display control.

If all monitored blocks 13 are operational, then for each circuit on display unit 11, a zero value of the adder 6 is displayed.

If at least one monitored block 13 failed, then in display unit 11, the value of the state of the sum of the torus 6, corresponding to the failure of one or several monitored blocks .3 (. Thus, all monitored

logical blocks 13 are checked at the same time, and the time of control does not depend on the number of controlled circuits and is equal to the time of control: one logic circuit.

The application of the invention makes it possible to draw a conclusion about the serviceability of the entire batch of logical blocks, as well as to reduce the time of control of a group of single-type logical blocks.

Claims (1)

DEVICE FOR MONITORING LOGIC BLOCKS, containing a clock pulse counter, adder-subtracter, display unit, the output of the adder-subtractor connected to the information input of the display unit, characterized in that, in order to reduce the monitoring time of a group of the same type of logical blocks, a register is entered, sum modulator two, trigger, two elements Й, group of elements And, group of combiners, clock generator, and the output of the clock is connected to the first input of the first element And, the output of which is connected to the clock input of the adder-subtractor and the input of the clock counter the outputs of which are connected to the inputs of the controlled logic blocks and the inputs of the second AND element and the first inputs of the corresponding elements AND groups whose second inputs are connected to the corresponding outputs of the register, the outputs of the elements AND groups are connected to the inputs of the adder modulo two, the output of the second element 'And is connected to the zero input of the trigger, the single input of which is the trigger input of the device, the zero and single outputs of the trigger are connected <g respectively to the control input. the indication block house and the second input of the first element And, the information inputs of the adder-subtractor are connected to the outputs of the combinational adders of the group, the inputs of which are connected to the corresponding outputs of the controlled logic blocks, the output of the adder modulo two is connected to the input of the sum (difference) of the adder-subtracter. \ SU <"1049913> 1 1049913 2