SU506909A1 - Buffer storage device - Google Patents

Description

The output of the element “OR 12 is connected KO | to the run of the counter 13 and through the element of delay | 4 to the INPUT 15 of block 6, and the inputs to the outputs of the elements“ And 9 and 10, one inputs of which are connected to the outputs 7 and 8 of block 6, and the Other entrances with control tires 11 and 30.

From decision block 1 According to the commands of synchronization block 2, all the samples are sent to the buffer memory 3, regardless of whether they are redundant or not. The selections are recorded in the input register 4. If the sample is not redundant, then a resolution potential is applied to the bus 30.

The control unit 6, made, for example, in the form of a reversible meter, determines the filling of the cells of the accumulator 20. If all the cells are filled, then at outputs 7 and 8 there is no resolving potential, if the device is empty, then at outputs 7 and 8 there is resolving potential, and in the remaining cases, the resolving potential is only at the exit of the resolution of the zashis resolution 7.

Potentials from output 7 (supplied to the input of element "AND 9, to another input of which potential is supplied from bus 30. Potentials from output 8 to input of element" I 10. At the same time as recording information to input register 4, bus 11 appears going to the inputs of the elements "AND 9 and 10. At the output of the element" OR 12, a pulse is formed either when a non-redundant sampling and incomplete filling of the memory device, or when the memory is empty.

12 enters the counter 13 and through the delay element 14, which is equal to the response time of the counter 13, to the input 15 of the control unit 6 and starts the shapers of the 16 and address 17 write currents.

Thus, an entry is made to the accumulator 20.

In the polling mode, the counter 21 receives a pulse from the polling generator 22. After passing the delay element 23, the pulse arrives at the subtraction input 24 of the control unit 6 and after 1 corresponding key element 25 goes to the address polling pane 26. The resulting bus code reads as a result

27 after amplification in the read amplifier 28 enters the output register 29.

Claims (1)

Invention Formula A buffer storage device containing counters connected respectively through key elements and address current drivers to a drive connected to a discharge current driver and read amplifiers, a polling generator, connected to one of the counters, the control unit and the delay elements, characterized in that, in order to simplify the device and increase the reliability of its operation, it contains the elements "AND and the element" OR, the output of which is connected to the input of another counter and through the delay element to the input of the control unit, and the inputs to the outputs of the And elements, some of the inputs of which are connected to the outputs of the control unit and others to the control buses of the device.