SU481851A1 - Digital frequency meter - Google Patents

Description

one

The invention relates to the field of measurement technology.

Known digital frequency, whose work is based on a two-stage

 method of measuring low frequency signals

 The known digital frequency counter contains a decade clock ratio

: And the measured frequency, decade pulse counter clock frequency (scaling circuit), decade time counter meas; rhenium pulses of the clock frequency and frequency multiplier associated with the buses of the controller with parallel outputs of the counter frequency ratio, frequency inputs; dami with pulse counter outputs

clock frequency, and the output - with the input of the time counter. The counting inputs of a frequency ratio counter, a clock counter, and a time counter output are associated with a timing and control circuit,

The disadvantages of the known frequency meter are a rather narrow frequency range and a complex structure.

To extend the frequency range

and simplify, the proposed frequency meter is equipped with two counters - shift registers, a decade control dual frequency drive, a reversible counter with an encoder and an OR circuit, with nejv counter - a shift register, an intermediate register with code transfer gates switched on at the inputs, a decade control splitter and the shifter counter-register is connected in series, the shifter-p & shifter outputs are connected to the reversible counter inputs, the outputs of the key circuits are connected to the inputs of the counters-registers gayuschih, output of OR circuit is connected to the input of one of schetchikovregistrov and input - to the output of the isolation circuit integer periods measured in my frequency and to the output of decade upravrl emogo divider respectively.

The drawing shows a functional diagram of a digital frequency meter.

The frequency meter consists of counters p & histra 1 and 2 shifting, controlled divider 3 key circuits 4 and 5, schemes

6 allocation of the chained number of periods of the measured frequency, intermediate register 7, code transfer valves 8, reversible counter 9, encoder Yu, switches 11, 12 and 13, time counter 14, valve 15, synchronization circuit 16, digital display unit 17, measurement results and indicate the position of the comma and the delay element 18. Each of the shift register counters contains a decade counter 19, gates 20, a binary counter 21, and a decoder 22. The managed divider contains a one-decade controlled divider 23, a ten-day multiplier 24 and a prohibition circuit 25. The allocation circuit of a small number of periods contains key circuits 26,27 and a delay element 2 8 (the schemes OR are marked in the drawing).

Frequency works as follows. With the arrival of the pulse signal, the start of the frequency meter opens the key circuit 26 of the circuit 6. selecting the whole number of periods and simultaneously in the roar | A gray counter 9 from the outputs of the encoder 1O is written the binary code of the number

R, m-k - r,

where fn is the number of decimal places of the counter-register 2; C ,, is a natural number or zero,

determined by the position of the switch 11.

Pulses of measured frequency F; from the output of the synchronization circuit 16, they begin to flow through the controlled input of the key circuit 26 to the output of this circuit. The synchronization circuit 16 realizes the attachment of the pulsed asynchronous signal of the measured frequency FX to the pulses of the reference frequency Fg, and also ensures the synchronous operation of the main nodes of the frequency meter. The first pulse, which appeared at the output of the key circuit 26, opens the key circuit 27. Since the delay time of impulse / pulse signals by the delay element 28 is longer than the duration of the pulses output from the key circuit 26, the first and mic on the output of the key circuit 2 7 do not pass.

Pulses from the output of the key circuit 26 through the additional output of the circuit

6 allocations of the integer number of periods

They also sink to the control input of the key circuit 4 and through the switch 13-a, and the corresponding input of the time-measurement setting and the start-up of the time counter 14. The first pulse, which occurred at the additional output of the whole period allocation circuit 6, starts j

the time counter 14 opens the key circuit 4, from the output of which the pulses of the reference frequency Fg begin to arrive at the input of the counter-register 1 At the opposite output of the time counter 14. a negative impulse signal of duration appears

iKi

ST.

1-10

sec

t,

where K is a natural number or-zero.

determined by the position of the switch 13. This signal goes to the control input of the valve 15, whereby the valve 15 is closed. The second and subsequent frequency pulses p; (from the output of the key circuit 26 through the controlled & key input of the key circuit 27 are fed to the main output of the allocation circuit of an integer number of periods and then to the controlled input of the valve 15 and to the counting input of the counter-register 2. After time interval T at the inveron output of the time counter 14 a positive impulse-potential signal appears, as a result of which the valve 15 opens. The next impulse that occurs after the time counter stops working at the output of the allocation circuit 6 is the number of periods passes through the open valve 15 to the inhibitory inputs of the key circuit 4 and the allocation circuit 6 of an integer number of periods, to the first control input of the key circuit 5 and to the controlled inputs of the code transfer valves 8, as a result of which the key circuit 4 and the allocation circuit 6 a whole number of periods are reset, the key scheme 5 is prepared for operation and the transfer of a content account is made

chip register 2 to the intermediate register 7. Let the pulse 15 at the output of the gate 15 to the input of the counter of the register 2 pass into pulses (tt -

the number of full frequency periods, V

In this case, key scheme 4 will be from, - open, during the time interval t sec, and therefore, the input of counter-register 1 will pass

 . N, tr3 n

pulses of the reference frequency F

Counters registers 1 and 2 implement the operations of pulse counting and shift of the counting results. In the initial state of the counter-register 2, a signal is received from the first output of the decoder 22, the corresponding code. Gate 20, the output of which is connected to the highest bit input of m - aracle decade counter 19, will be open, and the remaining 2 O gates will be closed by signals corresponding to the O code. The pulses of the source of counting pulses start to flow through the controlled input of the open valve to the counting input the older bit of the decade counter 19. Overflow pulse of the decade of the older bit of counter 19 goes to the counting input of the same decade and to the counting input of the counter 21. Counter 21 records the number of overflows, the decade of the older bit of counter 19, Consequently, after the L th overflow of the decade of the most significant bit of the counter 19, the source of the counting pulses will be connected to the counting input of the CH-I th bit of this counter, the highest bit of any number recorded in the meter 19 will always be in the most significant bit. This counter, therefore, the result of counting the number of periods of the measured frequency F will be represented in the counter 19 of the counter-register 2 in the following form:. p is the number of decimal digits of the number C. Since the number of decimal digits of counter-register 1 is equal to (W +1), it is obvious that the result of counting the number of periods of the reference frequency Fn by the counter will be represented in counter 19 of counter-register 1 as the number nFj g where S is the number of tenfold The ratios of the number N, At the end of the work of the counters-registers 1 and 2 from the outputs of the decade of the highest bits of these counters, the summing and calculating inputs of the reversing counter 9 will be received respectively (S-1) and (G-1) pulses, therefore the reverse counter 9 will be fixed to a number, + (S-1) -lr-l)) 7H-sr-K2, -Z. After transferring the number Q to the intermediate register 7, the code inputs of the controlled divider 3 will receive signals corresponding to the binary-decimal codes of the numbers P and O,. The principle of operation of the controlled division 3, formed by up1:) an admitted 23 decade divider 23 with the inhibition ban 25 at the input, and at the output the sequentially connected one-decade multipliers 24 are as follows. The numbers recorded in the counter-register 1 and intermediate register 7 can be written in the form of polynomials P., 10 - .. F, tn-Z10 10 - ..,, lO Mm .. 0 "(i49, where P is O- are the numbers represented by binary-decimal codes in the i-th decades of the counter-register 1 and the intermediate register 7. Each decade of the multiplier has two main and one auxiliary outputs and implements the following mutually independent multiplication factors specified by the i Correct fraction -K - gth. Frequencies on the first and second main and auxiliary outputs of the multiplier will be respectively equal. D 10 BK, HL I BX 10 OUT.E 3 8X-10 BX where P is the input frequency of a one-decade multiplier. Since the auxiliary output of each previous decade of multiplier 24 is connected to the input of each subsequent decade, and outputs of issuing codes of the fn younger order { TS 1) the bit counter of the chick register 1 and the outputs of the issuance of codes Ш of the bit intermediate register 7 are connected to the inputs of the reception of the codes of the corresponding decades of the multiplier, the common coefficients of the multiplier are IT1-11 "(iitiJO i: ilZili- M- 10 1, io., .- -aiioMoo a pulse repetition rate from combined feathers s and second combined outputs of the multiplier will correspond to values of FflblX. EXIT D2E EXIT D15 out va va ebixAas u, d23

7

where BYH.D.23 pulse repetition rate at the output of the single-decade divider 23,

The first outputs of the decade multiplier

24connected to banning circuit input

25 ban, realizing the operation of frequency subtraction, therefore, from the output of the prohibition on the input of the single-decade divider 23 pulses will be received

with a repetition rate equal to

.F.

ftK L4fe

.dge .yi vh.AZ Q you) (. A23,

where RVH.D.Z - pulse repetition rate at the input of the controlled divider 3; 5in.d.23- pulse repetition rate at the input of a single-decade divider

23.

Since the outputs of the issuance codes of the decade

the higher bit of the counter-register 1 is connected to the inputs of the reception of the single-decade controlled divider 23, then the divider of the divider 2 3 will be equal to the number Pfj, and the pulse repetition frequency from the output of this divider to the input of the multiplier 24 will be

equals

W.dgs

out dgs

m

Hjm, considering that

m

Rrtu

8H.DZ

EXIT A23

gp

ten

It is possible to write

tri

.daz r vh.dz

The pulse repetition rate of the incoming and combined second outputs of the multiplier 24, i.e. from the output of the control divider 3, will be equal to

p-v f-t

.Aaz

Out.r, 3 .A-i - P

log in

3 realizes therefore the divisor

The fractional division ratio of the form is 1, the numerator and denominator of which are represented by binary-decimal codes. It is obvious that after transferring the contents of the register 2 counter to the intermediate register 7, the division ratio of the controlled divider 3 is automatically determined by the Ge.

K-L-ii

equals

 n The output pulse signal of the valve 15 through the delay element 18 is also fed to the outputs of the decade of the counter of register 2 and through the switch 12 to the output of setting the time of measurement and start of the time counter 14. Counter 8

register 2 is reset and a vryumeni counter is started, with a positive potential signal with a duration of up to

-Is about

where k „- natural

the number or zero is determined by the position of the switch 12. This signal is fed to the second control input of the key 10 circuit 5, as a result of which the source of the reference frequency is connected via the controlled input of this circuit to: & the progress of the controlled divider 3. Obviously the pulse repetition frequency, coming from the output of controlled divider 3 to the input of counter-register 2, will be equal to

RE Oh, s-r-1

Ex.AZ k7 p fE FX

0 Key scheme 5 is in open communication during the time interval, therefore, I 1 is passed to the input of the register 2 counter (I -TG -T 1L -a output.A3 l

5 impulsovs. The result of the counting in counter-register 2 is recorded as a number .-) -d fS-1

N3 Yu.

where t is the number of decimal digits of the number 0 NO at the end of the counter-register 2 operation from the output of the decade of the most significant bit of this counter to the BSSOJ subtractor of the reverse counter 9 will arrive (I - 1) pulses, so that in the reverse 5 counter 9 will be fixed number

() s-l-ki-f-l.

Since the coded outputs of the register counter 2 and the reversible counter 9

0 are connected to the inputs of the reception of the codes of the block 17 of the indication of measurement results and the indication of the position of the comma, the results of the measured frequency F will be presented on the digital display of the block 17

5 indications in the form of a decimal number code

m-i-s-i-kz

FX-IO

X vj

and the position of hall ch1; d will be fixed before (fTi-bfi - L- - f - 1) the younger bits of the same number.

0 The frequency meter allows measurement with an accuracy of up to S - (T - 1) decimal place, and the position of the most significant digit of the measurement result is recorded in the highest digit of the digital display unit.

Subject invention

Digital frequency meter containing switches, switchable counter

time, a digital display unit indicating measurement discrepancies and indicating the position of a comma, an allocation circuit for an integer number of periods of the measured frequency, a synchronization circuit, an intermediate register, with code transfer gates switched on at the inputs, two key circuits,; the gate and the delay element, which is due to the fact that, for the purpose of increasing functionality and simplification, it is equipped with two counters n registers that shift, decade-numbered, the Healer, a reversible counter with an encoder and an OR circuit, counter

shift register, hgome dgg register with switched on torsion codes, transfer codes, decadal controlled frequency divider and second counter shift register registers connected in series, outputs of tilt registers-registers connected to reversible counter inputs, outputs of key circuits are connected to counter inputs- of the shift registers, the output of the OR circuit is connected to the input of one of the counters-regis-wire, and the inputs to the output of the allocation circuit of an integer number of measured tciotods and to the output of the decade controlled divider frequencies, respectively. T.