SU1233142A1 - Device for calculating direction cosine matrix - Google Patents

Abstract

The device relates to the means of computing and can be used in modeling the dynamics and control of flights of aircraft. The purpose of the invention is to increase accuracy. The device contains an interface block, a register memory block, a control unit block, four variable calculation units Xd, 7, Lg, Lz, respectively, three calculating blocks of diagonal cosines Cn, Cjj, € 53 SOOT and six blocks of calculating off-diagonal cosines C ,, С ,, С, C, zj, С „, С, 2, respectively. 8 il. with s

Description

The invention relates to computer aids and can be used in modeling the dynamics and control of flights of aircraft.

The purpose of the invention is to improve accuracy.

FIG. 1 shows a block diagram of an apparatus for calculating an array of cosine guides; tia fig. 2 is a block diagram of an interface unit; in fig. 3 - command format; in fig. 4 is a block diagram of a register memory block; FIG. 5 is a block diagram of the control unit} in FIG. 6 is a block diagram of a variable calculation block; FIG. 7 is a block diagram of a diagonal cosine calculation unit; in fig. 8 is a block diagram of a non-diagonal cosine calculation unit.

The block diagram (Fig. 1) contains the block 1 of the conjugation, the block of the 2-register memory, the block 3 of control, blocks 4-7. Variables calculation, blocks 8-10 calculating diagonal cosines, blocks P-16 calculating off-diagonal cosines, input control bus 17, input 18 and output 19 information buses, bus 20 O), bus 21 output} (the bus 2 2 input A, W.NI 23 control, bus 24 conditions, the first to fourth inputs 25-28 and the first sixth outlets 29–34 of the first interfacing unit, first to seventh inputs 35–41, and first to eighth outputs 42–49 of the second register memory 2, first to third inputs 50–52 and the first-tenth outputs 53-62 of the control unit 3, the first-twenty third inputs 6385 and the first-fifth outputs 86-90 of the block, the number of the variable L;, the first-twenty fifth inputs 91-1 5 and output 116 of the diagonal cosine calculating unit, first-sixteenth inputs 117-132 and output 133 of the non-diagonal cosine calculating unit. The block diagram of the conjugation block I (Fig. 2) contains a switch 134, a command register 135, a register 136 data, decoder 137 of the sample, buffer register 138 with open collector, information input 139, control input 140j | the first 141 and the second 142 switch outputs, the parallel write input 143 to all bits of the command register, except the first one, the 144 write input to the first command register bit, the command register write control input .145, the command register synchronization input 146, 147 ninety-nine output bit register command, output 148 of the tenth bit command register, output 149 of all bits of the command register, outputs 150-155 of the eleventh to the fifteenth bits of the register of commands, input 156 1) Register data., input 157 control register data recording, input 158 data register sync, you run 159 of the data register, inputs 160-165 and the first-third outputs 166-168 of the sample decoder, input 169 of the control for the buffer GO register with an open collector and input 170 of the buffer register with the OPEN collector.

Fig. 3 shows the format of the instruction that is stored in the instruction register 135. The first (most significant) bit is set by the control device signal from control block 3 and means Run / Stop, the content of bits from the second to the eighth is insignificant, the ninth bit. Starting starts the control machine to the initial state, the eleventh bit. writing to register 2 of register memory of data register 136, twelfth bit Reading controls reading to output data bus 19 of results obtained in one of the cosine calculation modules P-16, no active values (1) in these bits, the command register contents 135 commands are written to bus 19, the thirteenth, sixteenth | bits which contain the address of the register of the memory or the cosineus calculation unit in the positional code.

The block diagram of register register block 2 (FIG. 4) contains registers 171-178 for storing variables and, s, magnitude: variables H, variables,, (l AZ, respectively, first to fourth multiplexers 179-182, elements OR 183 -186, register information input 187, register write control input 188, register output 189, first 190 and second 19; control inputs of the multiplexer, first 92 and second 193 ir forms with the input and output 194 of the multiplexer.

The block diagram of the control unit 3 (Fig. 5) contains the first to fourth E-triggers 195-198, the decoder 199 states, the counter 200 clocks clever3

the same number, the shift number counter 201, the decoder 202 multiplication ends, the decoder 203 shifts, clock generator 204, AND 205-209 element, signal decoder 210 Signal element OR 211, AND element 212, OR elements 213-2 16.3) input 217 trigger, C input 218 flip-flop, trigger reset input 219, trigger output 220 first-third input bits of the state decoder 221-223 (first - least significant bit), first-eighth output bits of the state decoder 224-231 (first - low-order d) counter synchronization input 232, counter reset output 233, counter +1 234 input, counter output 235 ik, input 236 and direct 237 and inverse 238 outputs of the expander decoder, input 239, second input 240, first direct 241 and inverse 242 outputs, and second direct output 243 of the decoder 203 offsets, first 244 and second 245 outputs of the generator 204 clock signals .

The variable calculator block (FIG. 6 contains switches 246-248, first-third combinational adders 249-251, multiplexer 252, partial sum register 253, multiplier register 254, AND elements 255-260, information input 261, first 262 and second control inputs and output 264 of the switch, inputs 265 and

266 combination adder, input

267 transfer to the cd bit of the combinational adder, the output 268 of the combinational adder, the first 269 and the second 270 information inputs, the first 271 and second 272 control inputs and the multiplexer output 273, the parallel recording input 274, the left shift input 275 and the partial register input 276 amounts

inputs 277-280 control reset, shift right, shift left and register entries, respectively, output

281 right shift of this register, I

output 282 of the register of partial sums, input 283 of the shift of the multiplier register, input 284 of parallel recording in all bits except the minor, and input 285 of the synchronization of this register, inputs 286-288 of recording control in all bits except the younger, and reset the minor, shift to the right and shift to the left, respectively, of the register;

5 S 15 20 25

about

g

0 5

five

 424

the gistra, direct 290 and inverse 291 outputs of the last but one register bit of the multiplier, direct 292 and inverse 293 outputs of the last (lower) bit of the register multiplier.

The block diagram of the diagonal cosine calculation unit (Fig. 7) contains the first to fourth switches 294-297, the first to fourth combinational adders 298-301, a register

302 particle sums, buffer register

303 with open collector, elements And 304-311, information input 312

and the first 313 and second 314 control inputs of the switch, the output of the 3I5 generator, the inputs 316 and 317 of the combinational adder, the input 318 of the re-. nose to the low-order bit of the combinational adder, adder output 319, input 320 of parallel writing to the partial sums register, input 321 syncronization of this register, inputs 322- 324, respectively, of the reset, write and shift control of the partial sums register, output 325 of this register, a buffer register with open collector control input 326, information input 327 and buffer register output 328.

The block diagram of the off-diagonal cosine calculation unit (FIG. 8) contains the first 329 and second 330 switches, the first 331 and second

332 combinational adders, register

333-part sums, buffer register

334 with open collector, And 335-338 elements, information input 339, first 340 and second 341 control inputs and switch output 342, inputs 343 and 344 of a combinational adder, transfer input 345 to the lower rank of the adder, output 346 of the adder, input 347 parallel recording of the register of partial sums, register synchronization input 348, inputs 349–352, respectively, of control reset, com, record, shift right and shift register, output 353 of the register, control input 354, information input 355 and buffer register v6sod 356.

The device works as follows.

The matrix of the cosine guides is calculated using the Rodrig – Hamilton parameters:

J

C ,, (Luo, La)

C, 2t- A, Aa -A.lO C, r2 (, i A, J-,

) l 11)

(-AL, .C ,, ,, 2U ,, C, (- X, 0.4 L COS, ..

The Rodrigues-Hamilton parameters are related to each other by a system of differential equations:

(,. +) / 2

1 (,,) l il, A, -tO ,,) | 2

 (w, c0.j ,, - co,.,) / 2.

For determination at time t, the value of the CO variables at the time t and the initial values of the variables L are required; at the moment of time.

To solve the systems (1, the Euler algorithm is used, where

A (t) ft «() + H Ao-, X, (t) - A.,, H (t)), A, (t). () + H A3}

“I at the same time and - mar integration, a

; is determined from a system of equations, n is selected as a number equal to 2 J when 3 -1 multiplication by H is reduced to a shift by a certain number of bits. Since when multiplying Ui L; result. is in the multiplier register 5, then to combine the alignment of the result with multiplication by n 2, use the equivalent left shift by the value of .n-k-, where n is the information presentation width.

The operation of the device proceeds in several stages: loading the initial values of the variables -Y- into the registers of block 2 of the register memory from the external computing system before starting the numerical integration, loading the value of H and variables 03j into the registers of block 2 of the register memory and outputting from the device through block 1 . the mates of the calculated direction cosine matrix

Writing data to the registers of block 2 of a register memory from an external computing system and reading cosines are controlled by block I: mates, and the course of calculations is controlled by block 3 of control. The interface unit 1 controls the operation of the control unit 3, translates the control of the automaton into the initial state, giving a signal to the output of 31 bp, 1 of the interface, and starting the control automaton, issuing a trigger signal to the output 30 of the unit 1 wives

10 To perform actions at the first stage, the external computing system issues to the first and second bits of the thrashing bus 17 signals and a command to write the variable Lc to the register

15 176 for variable storage. This command is passed by switch 134 to output 14, and the sync pulse at the fourth level of bus 17 is written to command register 135. At that, the external computing system generates a signal for the third bit of the ShIRSH 17, shown in the signals from the first two bits of this bus, and provides information on the variable information of the input information bus 18. This information is passed by the switch 134 to the output 142 and is recorded on the clock signal in the register 136 data. The bits of the register 135 of commands are decrypted by the decoder 137 of the sample and in the corresponding level of the output 166 of this decoder a signal of the sample appears, which from the output 33 of the interface 1 enters the input 36 of the unit 2

5 of the register memory to the corresponding bit connected to the input 191 of the multiplexer 179 and through the element OR 183 to the input 188 of the control of the recording of the register 175 for storing the variable.

0 The information from output 32 of the interface unit is transmitted from input 193 of multiplexer 179 to output 194 and the E register 175 is written. Similarly, TI 1 is written to register 176, -5 to register 177., A - to register 178. First, command register 135 is written the corresponding command, then to data register 136 — this,. and then it is rewritten to the corresponding register in block 2 of the register memory.

The actions in the second stage are similar, but the commands give a Reset signal. As a result, Those B register 171 recorded variable "i, in register 172 - hell, in register 174 - the value of H, in the register

73

with,

In the third stage, the external computing system writes to the register 138 a command containing the Start signal. At the previous stage, the control automaton is reset (triggers 195-198 are reset by a reset signal at input 51 of the 3.control unit received from output 31 of the interface block i, at the first output level of 224 degrader 199 states by wils signal). Now, when the control automaton goes into the next state, the trigger 198 is set, which leads to setting 1 in the first 1 bit of the register of 135 commands with a signal at input 27 of the gateway block, to reset the counters 200 and 201 in block 3 of the control . At the outputs 56 and 61 of the control unit 3, the control signals appear, along which the multiples 252 in the blocks 4-7 pass the values of the variables I; from the outputs 86 of these blocks, which were received via the bus 21 output from the outputs 46-49 of block 2 of the register memory. This data is recorded in all bits except the low-order in the multiplier registers 254. The partial amount registers 253, 302, and 333 in blocks 4-16 and the low-order bits of registers 254 in blocks 4-7 are zeroed out.

In the next cycle of operation of the control automaton, the signals are present at the outputs 57 and 60 of block 3. Through the control bus 23 they enter blocks 4-16, where the inputs of the And 255-260 elements in blocks 4-7, the inputs of the And 304-311 elements Blocks 8-10 and elements entering And 335-338 in blocks 11-16 through the bus 24 conditions receive the two lowest bits of the registers 254 multipliers in the paraphase code from the outputs 87-90 of blocks 4-7. The control signals of the And elements are used to obtain products in registers 253 partial sums in blocks 4-7, registers 302 in blocks 8-10, and registers 333 in blocks 11-16. Blocks 4-16 are constructed in such a way that, when changing the lower-order bits, the multiplier from 1 to O multiplicates from the inputs 63-g65 in blocks 4-7, the inputs 91-94

esf.

In blocks 8-10 and inputs 117 and 118 in blocks 11-16 passes through the corresponding switches without changes, when changing the low-order bits from

five

5 10 5 20 0

5 0 5 0

O into 1 input code is inverted on the corresponding switch and fed to the adder, and 1, which is equivalent to subtracting the multiplicand, enters the transfer input to the 4th bit, respectively, of the 3 rd matrix. The switches are controlled by the corresponding elements AND, the multiplication with the partial sum is provided by the signal from the output of the corresponding odd element, and the subtraction is done from the output of the corresponding even element, if the lower bits of the multipliers are equal, the signals at the output of the corresponding elements The retatop appears the zero code. After performing the described actions, the data is added on the combinational adders and written to the partial sum registers.

The output of the counter 200 multiplications is decrypted by the multiplier 202 decoder 202. If the multiplication is completed, the decoder outputs a signal at output 237, and if not, output 238. In this case, the next clock of the control automaton, at output 58 of unit 3, a control signal appears, which in all registers of blocks 4-16 there is a modified right shift, with the low-order bit of register 253 output 281 being transmitted to input 283 of register 254. Counter 200 is incremented by one. After that, the control automaton returns to the previous state and the described actions are repeated until the output signal appears. 237 of the decoder 202. Then the control automaton goes to the next state, where the shift number counter 201 increases by one and in blocks 4–7 and 11–16, the registers are shifted by one bit to the left, since control signals from the outputs 59 and 62 of block 3 are sent to their control inputs. The highest bit of register 254 from output 289 is fed to input 275 of register 253 In this cycle, the signals from the output of the 235 counter 201 post They are fed to the input 239 of the decoder 203, where they are compared with the value H received at the input 240 of the decoder 203 from the input 52 of block 3 from the block 2 of the register memory. If the output is 243

the decoder 203 wits a signal indicating equality, the control machine in the next cycle enters the next state, if not, remains in it, but the signal from the output 62 of the block 3 cn -1 can be changed as the counter state 201 changes and disappears the signal from the output 243 of the decoder 203. Thus, there is a shift to the left H times in blocks 4-7., once in blocks, which is equivalent to y of numbers on H in blocks 4-7 and multiplying by two sums of products in blocks 11 -sixteen.

In the next state of the control automat, the signals are present at the outputs 60 and. 61 block 3. These signals in blocks 4-7 pass the variable from the registers of block 2 through multiplexer 252 to adder 250 and add this number to the contents of register 253 partial sum and then write the result to this register. In the next control state The automaton signal is present at output 64 of block 3. At 3TONry signal; 1lu multiplexers 179-182 in block 2 pass information on outputs from inputs 38-41 of block 2, to which outputs 86 of blocks 4 are connected via bus 22 to input 7 -7 respectively. The control inputs for recording registers 175-178 through the OR elements 18.3-186 receive a signal from the output 54 of block 3 through the input 37 of block 2, and the values calculated at this step and contained in registers are written in parallel to registers 175-178. partial sums of blocks 4–7. In block 3, trigger 198 is reset, which leads to zeroing of the first bit of the register of 35 commands. The start command is removed by the external computing system at the time of operation of the device. By the end of the third stage, in the registers of blocks 8-16 there are guiding portions e.y, and in the registers of block 2 - the calculated values il; .

During computations. The external computing system executes the command register reading command, which results in a signal that causes the buffer register 138 with an open collector to the active state in the code 168 of the sampler 137. Then on the output information type 19 there is information from the command register. Upon completion of the computation, the state of the first bit of the instruction register is changed, which signals the possibility of cosine input. The outputs of the registers in blocks 8-16 are connected to a buffer GM registers with an open collector, which are bit-wise connected to input 28 of the block and are output 29 of the same block.

At the fourth stage, the external computing system outputs the calculated cosine values from the device, for which it issues a preliminary cosine reading command with the corresponding address. The open-collector buffer register is activated, which is connected to the corresponding bit of output 167 of decoder 137 of block I, and the information is entered into the external computing system.

After the cosines are entered, the device, at the command of the external computing system, continues to work either from the first or from the second stage, using in the latter case the values calculated at the previous step in the third stage as the initial values.

Claims (1)

Invention Formula A device for calculating a matrix of cosine guides, containing a register memory block, a control block, characterized in that 5 with the aim of predicting accuracy, four blocks of digits and variables 5 are inserted, three blocks of diagonal cosines calculation, six blocks of non-diagonal calculations a sinusus, the register memory block contains a storage register of value Tsaga, three storage registers of angular velocity values, four change storage registers, four multiplexers, whose outputs are connected to information nnym inputs hrai registers: eni Move Shikh ipformatsionmy ,, wherein the input device to the sub, to the data inputs pyuchen regisrov storing angular velocity values and. step values and the first information inputs of the multiplexers, the first four bits of the input control input device data are connected respectively to the control inputs by writing the first, second, third registers of angular velocity values and the step size register, and the last four bits are connected respectively to the first control first, second, third, fourth null type and, respectively, to the first inputs of the first, second, third, fourth OR elements whose outputs are connected respectively to the control inputs of the first, second, third, fourth variable storage registers, the control unit contains four flip-flops, a state decoder, a multiplication count counter, a shift number counter, a multiplier ending decoder, a shift sync generator, six AND elements, five OR elements and a write decoder, with the outputs of the first, second, and third flip-flops connected to the inputs of the state decoder, the first output of which is connected to the inputs of the zero-state setting The multiply count counter and the shift number counter, the counting inputs of which are connected respectively to the fourth and fifth outputs of the state decoder, the synchronization inputs of the counter, the number of shifts and the multiplier counter, are connected to the first output of the clock generator, and the outputs of the multiplication counter and the number counter shifts are connected respectively to the input of the decoder of the end multiplier and the first group of inputs of the shifter of the shifts, the second group of inputs of which is connected to the bit outputs of the storage register in The values of the step of the register memory block, the forward and inverse outputs of the decoder of the multiplication end are connected respectively to the first inputs of the first and second And elements, to the second inputs of which the third output of the state decoder is connected, the first forward and inverse of the shift decoder are connected. respectively, with the third inputs of the third and fourth elements I, the second inputs of which are connected to the fifth output of the state decoder, the third and sixth outputs of which are connected respectively to the first and second inputs of the recording decoder, the third input of which is connected to the first output of the clock signal generator, the fifth output of the state decoder is connected to the first input of the fifth AND element, the second input of which is connected to the second forward output of the shift decoder, the second output of the state decoder connected to the information input of the fourth trigger and the first input of the first element OR, to the second input of which the sixth output of the state decoder is connected, the seventh output of which is connected to the first input of the second element and OR, the second input of which is the device installation input to the initial state, the output of the second element OR is connected to the installation input to the zero state of the fourth trigger, the device start input is connected to the first input of the sixth element AND, the second input of which is connected to the first output of the decoder states, and the output of the sixth AND element is connected to the first input of the third OR element, the second and third inputs of which are connected respectively to the outputs of the second and third AND elements, the output of the third OR element is connected to the information input of the third trigger, the outputs of the fourth and fifth elements OR are connected respectively to the information inputs of the first and second triggers, the first, second and third inputs of the fourth element OR are connected to the outputs of the first element AND, the fifth and sixth outputs of the state decoder, the second, the third and sixth outputs of which and the output of the second element AND are connected respectively to the first, second, third and fourth inputs of the fifth OR element, the trigger synchronization inputs are connected to the second output house clock generator, wherein the setting inputs to the zero state of the first, second and third flip-flops soedi-- Nena to the input device installation In the initial state, the seventh output of the state decoder is connected to the second control of the multiplexer inputs and OR elements of the register memory unit. The variable calculation unit contains three switches, three combinational adders, a partial sum register, a multiplier register, a multiplexer and six elements And, the outputs of the first, third, fifth elements And are connected to the first control inputs of the first, second, third switches, respectively, the second control inputs of which are connected respectively to the outputs second, fourth, sixth elements And, respectively, with the transfer inputs to the lower order of the first, second, third combinational adders, the first and second inputs of the first combinational adder are connected respectively to the outputs of the first and second switches, the third Go switch is connected to the first information input of the multiplexer, the output of which is connected to the first input of the second Raman adder and to the input of a parallel  records in all bits: except for the low multiplier register, the second input of the second combinational, the adder is connected to the output of the first combinational adder, the output of the second combinational adder is connected to the first input of the third combinational adder, the second input of which is connected to the output of the partial sum register, the output of the third the combinational adder is connected to the input of a parallel record of the register of partial sums, the right shift output of which is connected to the right shift input of the multiplier register, the left shift output of which It is connected to the left shift register of the partial sum, the clock inputs, right shift control, left shift control of both registers are connected respectively to the first clock generator output of the fourth and the fifth state decoder of the control unit, the partial sum register and reset inputs of the last bit and parallel recording in all bits, except the last one, the register multiplier is connected to the output of the first element OR of the control unit, the control input of the parallel recording is registered the partial sum trap is connected to the output of the write decoder of the control unit; the first control input of the multiplexer and the first inputs of each element The variable calculation unit is connected to the third output of the state decoder of the control unit, the second control input of the multiplexer is connected to the second output of the state decoder of the control unit, the information inputs of the first, second, third switches are connected respectively to the outputs of the first, second, third value storage registers the angular velocities of the register memory block, the outputs of the first, second, third, fourth registers of storage of the variable register register block are connected to the second inst formation inputs of multiplexers, respectively, of the first, second, third, fourth variable calculation units, and outputs of the partial sum registers of the first, second, third, and fourth variable calculation units are connected respectively to the second information inputs of the first, second, third, and fourth multiplexers in the register memory block, moreover, the direct output k and the inverse output ki of the bits of the register of the multiplier (k is the width multiplier of the first block of the variable calculation block) are connected to the second and the third inputs of the second, fourth, sixth elements And, respectively, of the second, third, and fourth variable calculation blocks, the inverse output k-ro and the direct output (kt) of the register bits of the multiplier of the first variable calculation block are connected respectively to the second and third inputs of the first, the third, fifth elements And, respectively, of the second, third, fourth blocks, and the direct output of the k-ro and the inverse output of the (k -1) th register bits, the multiplier of the second variable calculation block are connected respectively to the second and t The first, fifth, and fourth elements of the first and third, fourth, and fourth calculation units of the variable, inverse output, and direct output (k-Ij-ro bits of this register are connected respectively to the second and third inputs of the third, sixth, first, and the first, second, and fourth blocks of the variables, respectively; direct output (k -) -. ro bits of this register are connected respectively to BTopobfy and the third inputs of the fourth, fifth, second And elements, respectively, of the first, second, and fourth calculation blocks of the variable, and the k-ro direct output and inverse output (kl) -ro bits of the register of the multiplier of the fourth block; variables are connected to the second and third inputs of the fifth, third, second elements AND of the first, second, and third blocks of the variables, respectively; the inverse output k-ro and direct my output (kl) -ro bit up this register is connected respectively to second and third inputs of the sixth, fourth, first elements And, respectively, the first, second, and third variable calculation blocks, the diagonal cosine calculating block contains four switches, four combinational adders, a partial sum register, a buffer register, eight AND elements, and outputs of the first, third, fifth seventh AND elements are connected to the first control inputs, respectively, of the first, second, third, fourth switches, the second control inputs of which are connected by cooTBeTCTBeftHo to the outputs of the second, fourth, sixth, and eighth elements AND, respectively About the first, second, third, fourth combiner adders in the lower-order transfer bits, the first and second inputs of the first combinational adder are connected respectively to the first and second commutators, the output of the first combinator is connected to the first admittance of the second combiner adder, the second input of which is connected to the output of the third combinational adder, the first and second inputs of which are connected to the outputs of the third and fourth switches, respectively, to the first and second inputs the four combinational adders are connected to the outputs, the register, partial sums and the third combiner adder, the output of the fourth combinational adder is connected to the input of the parallel register of the partial sums, output 5 O 0 five 0 which is connected to the input of the buffer register, the output of which is connected to the output of the block, and the inputs of the synchronization, right shift control, resetting the register of the first 1 gnum sums are connected according to the first output of the sync signal generator, the fourth bit output of the state decoder, the output of the first OR element the third output of the state decoder, which is connected to the control input, recording the register of partial sums and the first inputs of all elements AND of the diagonal cosine calculator, and The first, second, third and fourth switches of the diagonal cosine computing unit are connected respectively to the outputs of the first, second, third, fourth registers of storage of variables of the register memory block, the control inputs of buffer No. 1x of the first, second, third registers of diagonal cosine calculation blocks are connected respectively to the first the second and the third bits of the nine-bit input bus control read the cosines of the device, with the direct output of the last but one and inverse output of the last The first bits of the variable multiplier register are connected to the second and third inputs of the first elements, AND of each diagonal cosine block; the inverse output (k-i) -ro and the direct output of the k-ro bits of this register are connected respectively to the second and the third inputs of the second elements AND of each diagonal cosine calculating unit, the direct output (kl) -ro and the inverse output of the k-ro bits of the register of the multiplier of the second variable calculating unit are connected respectively to the second and third inputs Odes of the third, fourth, fourth elements And, respectively, of the first, second, and third blocks of calculating diagonal cosines, the inverse output of the (k- -1) -th and direct output of the k-ro bits of this register are connected respectively to the second and third inputs of the fourth, third diagonal cosine calculation blocks, direct output (kl) -ro and inverse output of the k-ro bits of the register of the third multiplier of the variable calculation block are connected respectively to the second and third inputs of the sixth, fifth, sixth elements AND, respectively, of the firstJ torogo, third blocks Calculating the diagonal cosines, the inverse output (k-) ro and the direct output of the k-ro bits of this register are connected respectively to the second and third inputs of the fifth, sixth, fifth elements And, respectively, of the first, second, and third blocks — the calculation of the diagonal cosines, and the direct output (kl) -ro and the inverse output of the k-ro bits of the register of the multiplier of the fourth variable block are connected respectively to the second and third inputs of the eighth, eighth, seventh elements Commerce And, respectively, of the first, second, and third blocks of calculating the di agonal cosines, inverse you, the stroke (kl) and the direct output of bits of this register are connected respectively to the second and third inputs of the seventh, seventh, eighth elements And the first, second, third blocks, respectively diagonal cosine computations. Moreover, the off diagonal cosine computation block contains two commutators, two combinational adders, a partial sum register, a buffer register, four AND elements, outputs of the first, third AND elements. inen respectively with the first control inputs of the first and second switches, the second control inputs of which are connected respectively to the outputs of the second, fourth elements AND and respectively to the transfer inputs to the lower bit of the first, second, combining adders, outputs of the first and second switches connected respectively to the first and second inputs of the first combinational adder, the output of which is connected to the first input of the second combinational sum of the torus J to the second input of which connect Isra partial sums vghoD second Raman podyushchen adder to the input of a parallel write register partial sums, the output of which sub-key n to the input buffer register,  the output of which is connected to the output of the block, and the synchronization inputs. shift control to the right, shift control to the left, resetting the register of partial sums are connected respectively to the first clock generator output, quarter-time output of the state decoder ,. the output of the fifth element AND, the output of the first element OR of the control unit, the third output of the state decoder is connected to the control input of the partial sums register and to the first input of each AND element of the off-diagonal cosine calculation unit, and to the input of the first switch of the first, second, third, the fourth, fifth, sixth, blocks of calculating off-diagonal cosines of the subcontrols, respectively, the outputs of the fourth, third, fourth, second, third, second pe1: isters of storing variables of the register memory, to the input of the second switch of the second, second, third, fourth, fifth, sixth blocks of calculating non-diagonal cosines are connected, respectively, to the outputs of the third, fourth, second, fourth, second, third registers of variables of the first block of register memory, moreover, the control inputs of the buffer register of the first, second, third, fourth, fifth, sixth of the nondiagnose cosine calculation units are connected respectively to the fourth, fifth, sixth, seventh, eighth, nineth of the ninth The main input bus control bus reads the device, the direct output (kl) -r and inverse output of the bits of the register of the multiplier of the first variable calculation unit are connected to the second and third inputs of the first, second, second, second, first 5 first, respectively elements And, respectively, of the first., second, third, even. grated, fifth, sixth blocks of calculating off-diagonal cosines, inverse output (kl) -H inverse output of the k-ro bits of the register of multiple. the second variable calculation block is connected to the second and third inputs of the third elements of the first and second blocks of calculating off-diagonal cosines, the inverse output (k-l) - ro and direct to; one k-ro bits of this register, respectively connected to the second and third inputs of the fourth element. In the first and second blocks of calculating the nondiagonal cosines, the direct output (kl) -ro and the inverse output of the k-ro bits of the register of the multiplier of the third block of variables, are connected respectively to the second and the third inputs of the third elements of the third and fourth blocks of calculating off-diagonal pulses, the inverse output (kl) -ro and the direct output of the k-ro bits of this register are connected respectively to the second and third inputs of the fourth elements of the third and third the fourth computing unit off-diagonal cosines, and the direct output (kl) -ro and inverse output k-ro bits of the register of the multiplier of the fourth variable calculation unit are connected respectively to the second and third inputs of the third elements of the non-diagonal cosines , the inverse output (k -) - ro and the direct output bit DON of this register are connected respectively to the second and third inputs of the fourth elements And the fifth and tttecToro calculation blocks of off-diagonal cosines, and the output all cosine calculators are a group of outputs from the device, with the output of the fourth trigger of the control unit connected to the signaling output of the device. one 0ta.5 .6 stsiiaso 2771/50 .Mirage 671Subscription VNIIPI USSR State Committee on affairs of “discoveries and discoveries P3035, Moekna, g-35, Raushsk nab., d., 4/5 Production and printing company, Uzhgorod, st. Project, 4