SU475622A1 - Priority device - Google Patents

Description

priorities; 4 and 5 - groups of schemes 6 and 7 - counters; 8 and 9 - groups of circuits 10 - pulse generator; 11 and 12 diagrams 13 - control trigger; 14 and 15 - weekend triggers; 16 and 17 — schemes 18 — trigger trigger; 19 - diagram 20-25 - device inputs; 26, 27 and 28 — device outputs; 29 —the bus connection of the zero output of the trigger 13; 30 and 31 - outputs of register 1 for wok; 32 and 33 — buses connecting the outputs of counters 6 and 7; 34 is a single output connection bus of trigger 13.

If it is necessary to access the device, the processors send requests from inputs 22 and 23 to the corresponding register 1 register. The number of register bits in the order is equal to the number of processors. Wake signals are sent at random times. The priorities of the processors are determined by the priority numbers, the codes of which are entered into the priority registers 2 and 3. The highest priority processor corresponds to the smallest (when choosing the subtractive counter type) or the highest (in the case of selecting the summing counter type) priority code. When the system is running, these codes may change during each priority assignment cycle in the system.

Groups of schemes “And 4 and 5 provide a census of priority codes into the appropriate counters and, 7 before the start of the next cycle of work. The type of meter can be summing or subtracting.

With the help of the circuit groups "AND 8 and 9, the clock pulses from the generator 10 are fed to the counting inputs of those counters that correspond to the processors that sent the signals to the register of the quotation. The counters are filled with pulses until an overflow pulse appears at the output of the counter containing the smallest (or highest, determined by the type of counter) priority code in the current priority assignment cycle.

The OR 11 circuit that assembles overflow signals, the OR 12 circuit and the control trigger 13 stop access from the generator to the pulse counters following the one that caused the counter overflow corresponding to the processor having the highest priority.

The output triggers 14 and 15 fix an overflow pulse at the single input and form a single signal at the corresponding output of the device.

The “OR 16, 17, busy trigger 18” and “And 19” circuits provide the initial and subsequent operation cycles of the device when signals arrive in the quotation register.

The device works as follows.

Signals from subscribers whose priorities are different and are determined by priority codes listed in priority registers 2 and 3 are served in register 1 for a wok. The initial start signal from input 24 is fed through the circuit OR 12 to the zero input of control trigger 13. At the same time, a single signal is generated at the zero output of the control trigger, which opens the AND 4 and 5 circuits, providing a copy of the priority codes to the input of the counters 6 and 7. At the same time, the signal from input 24 passes through the OR 16 circuit 18 busy opening it.

Circuit "I 19" is opened by a single pulse from the output of the trigger trigger and signals from outputs 30, 31 of register 1 of the application through the "OR 17" circuit, which assembles them, are fed to a single input of control trigger 13. At the same time, the zero signal locks the AND 4, 5 circuits, and the inverse signal from a single output (34) closes the busy trigger and opens those And 8, 9 circuits that receive single signals from outputs 30, 31 (trigger 18 is set to The Bits and the “And 19” circuit create the necessary delay of the signal from the output of the “OR 16 circuit for a time sufficient to write the priority codes from the priority register to counters 6, 7).

This opens the access of pulses from the generator 10 to the counting inputs of those counters 6, 7, which correspond to the subscribers who sent the signals to the register of the quota. The filling of the counter continues until the occurrence of an overflow pulse at the output of the counter corresponding to the highest priority.

When the overflow pulse arrives at the input of the OR 11 circuit, an output of the end of the operation cycle is generated at its output, which passes to the output 26 of the device to query the subscriber and through the OR 12 circuit to the zero input of the control trigger 13, transferring it to wherein the zero signal locks the AND 8, 9 circuits, preventing admission to the counters 6, 7 of the pulse following the one that caused the overflow of the counter corresponding to the most priority processor.

A single impulse from the corresponding counter is applied to one of the output triggers 14, 15, as a result of which a single signal is generated at a certain output of the device, and resets the corresponding

discharge register for the wok, withdraw from the queue selected for the app.

When the subscriber receives a response signal from the subscriber to the control input 25, the output triggers 14, 15 and counters 6, 7 are reset, and the busy trigger is reset via the OR 16 circuit by this signal. The signals from the outputs 30, 31 of register 1 can again be sent to the single input of control trigger 13, ensuring the start of a new cycle of operation of the device.

Subject invention

Priority device containing the register of the current, priority registers, counters.

pulse generator, AND, OR circuit, control triggers, busy triggers, output triggers, characterized in that, in order to increase the efficiency of using the device, the outputs of priority registers through the corresponding first groups of AND circuits, whose control inputs are connected to the zero output of the control trigger is connected to the recording inputs of the corresponding counters, the counting input of each of which is connected to the output of the pulse generator through the corresponding second group of circuits, the second inputs of the circuits "And the second group of connections us with a single output control trigger, the third inputs connected to respective outputs of the register for wok, counter outputs are connected to respective inputs of the register by control applications are, to the inputs of the first circuit "and OR

the unit inputs of the corresponding output triggers, the outputs of which are connected to the outputs of the device, the output of the first circuit OR connected to the output of the device and through the second circuit OR connected to the zero input of the control trigger, the single input of which is connected to the output of the circuit I, whose first input is connected to the output of the third OR circuit, the second input — with the output of the trigger trigger, the single input of which is connected to the output of the fourth OR circuit, the zero input — with the single output of the control trigger, the inputs of the third OR circuit us to register outputs for wok, inputs

priority registers, register of registers, control inputs of counters and output triggers, the input of the second OR circuit, and the inputs of the fourth OR circuit are connected to the corresponding inputs of the device.

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