SU474853A1 - Reverse shift register - Google Patents

Description

The invention relates to computing and discrete automation and is intended for the operation of forward and reverse binary numbers.

A reverse shift register is known, built on the basis of type D triggers, each bit of which consists of three / 5 triggers — one memory and two switching, and the / 5-memory trigger has one unit and two zero arms, controlled by reverse signals .

However, the presence of critical congresses of logical elements in a known reverse register can lead to a failure of the register.

The purpose of the invention is to improve the noise immunity of the device.

This is achieved by the fact that the proposed device contains a memory trigger in each bit, the first and second switching triggers performed on the AND-NOT elements, and differs from the well-known fact that each switching trigger is soda (the additional AND-NOT element forming the second zero shoulder switching trigger with to; full iBbiXioaoM zero and zero inputs. The single output of the first switching trigger is connected to one of the zero inputs of the second switching trigger of the previous register bit and

one of the additional zero inputs of the second switching trigger of the subsequent discharge. Zero and an additional zero outputs of the first switching flip-flop are connected to the single inputs of the memory flip-flop, a single output of the second switching flip-flop is connected to the zero input of the first switching trigger N A previous discharge and dsaoLNitelnym zero input of the first switching trigger nosleduyuschego discharge, the zero output of the second switching flip-flop is connected with a zero memory trigger input and with one of the zero inputs of the second switching trigger of the previous bit. An additional zero output of the second switching trigger is connected to one of the zero inputs of the memory trigger and to one of the additional zero inputs of the second switching trigger of a subsequent discharge. The zero input of the first switching flip-flop is connected to the single output of the second switching flip-flop of the subsequent discharge, the additional zero input of the first switching flip-flop is connected to the single output of the second switching flip-flop of the previous bit; and the first switching triggers of the next bit. Additional zero inputs of the second switching trigger are connected to a further zero and single outputs of the second and first switching triggers of the previous bit, respectively, one of the zero inputs of each of the switching triggers of each of the bits of the Ooadiibn register with SIG, ala “Ca: wig left, and one of the additional zero inputs of the same flip-flops is connected to the signal bus “Shift to the right.

FIG. 1 shows a diagram of three bits of the LS.TROY10T1va; FIG. Two of the bipeiMeH diagrams illustrating the functionality of the C | B1e device.

Each bit of the device contains a memory trigger (type R, S) on the elements AND-NOT / and 2, the first and second switching triggers on the elements AND-NOT 3-5 and 6-8, respectively, and the elements 3, 8 form single clerks these triggers, elements 4,7 - the main zero shoulders, elements 5, 6 - additional zero shoulders with the corresponding additional zero inputs and outputs.

The zero inputs of each switching trigger of each bit are connected with a thickness of 9 "Sdvng left, and the additional zero inputs of the same triggers - with the bus 10 of the signal" Shift right. Zero inputs and pre-zero zero inputs of switching triggers are connected to the bus // clock pulses. Bus 12 is fed to the additional zero input of the first switching trigger of the first bit, which feeds the direct code of the input information when shifted to the right. The inverse code of the input information during the shift to the right is fed to the additional zero inputs of the second switching trigger of the first discharge via buses 13 and 14. The direct code of the output information during the shift to the right is fed from the single output of the second switching trigger of the last discharge on output 15. The inverse code of the same The information is fed to the outputs 16 and 17 from the single output of the first and additional zero output of the second switching triggers of the same bit.

On bus 18, the zero input of the first switching trigger of the last bit is supplied with the direct code of the input information when shifted to the left; The inverse code of the same information is fed through buses 19 and 20 to the zero inputs of the second switching trigger of the same bit.

The direct code of the output information when shifting to the left is supplied from the single output of the second switching trigger of the first bit to the output 21; the inverse code of the same information is fed to the outputs 22 and 23 from the single output of the first and zero output of the second switching triggers of the first bit.

Connecting device outputs: To the appropriate input information buses, allows you to implement various ring counters. For example, when the output 15 is connected to the bus 12, and the outputs 16 and 17, respectively, to the buses 13 and 14, a ring counter with cyclic coding is implemented ((WITH sdIgam and Form) and: and to the right).

When the information is shifted to the right in all bits of the register, additional

zero shoulders of switching triggers, and the main zero shoulders are turned off. When the information is shifted to the left, the main zero shoulders of the switching triggers are turned on, and the additional ones are turned off. Connection

between register bits, provide control of switching each register bit with information from the corresponding adjacent bit, and this information can be changed only after

the end of the clock pulse. This algorithm of operation excludes critical components of differential elements of various bits. The register register itself is based on an asymmetric type T trigger, which is not

contains critical congresses of logical elements. Taking into account that the control information does not change at the time of the clock action, there is no need for internal interlocking connections between switching triggers within each register bit.

The register works without failures with arbitrary spreads of signal delay times in logic elements.

Timing diagrams illustrate the sequence of advancing two logical units through the three bits of the register to the right and left. The numbers of the time diagrams correspond to the numbering of elements and tires

The devices in FIG. 1. The indices I, P, and HI indicate that the I – N elements of 1/8 belong to the first, second, and third bits of the device (from left to right in Fig. 1).

The device circuit can be implemented

on the elements NLI-NOT without changing the connections between the elements.

Subject invention

A reverse shift register containing in each bit of a memory trigger, the first and second switching triggers performed on the AND-NOT elements, a single output of the memory trigger is connected to a single input of the first switching trigger, one, 1H1Ilic 1 EXT 01D "OTapioro Connected - a single input the second switching trigger, one of the zero inputs of each switching trigger is connected to the clock bus

pulses, characterized in that, in order to improve noise immunity, each switching trigger contains an additional AND NOT element, forming the second zero arm of a switching trigger with an additional zero output and zero

inputs, the unit output of the first switching trigger is connected to one of the zero inputs of the second switching trigger of the previous register bit and one of the additional zero inputs of the second switching trigger of the subsequent discharge, zero and additional zero outputs of the first switching trigger are connected to the single inputs of the memory trigger, the single output of the second switching trigger is connected to the zero input of the first switching trigger of the previous bit and with an additional zero the input of the first switching trigger of the subsequent discharge, the zero output of the second switching trigger is connected to the zero input of the memory trigger and one of the zero inputs of the second switching trigger of the previous discharge, the additional zero output of the second switching trigger is connected to one of the zero inputs of the memory trigger and one of the additional zero inputs of the second switching trigger of the subsequent discharge, the zero input of the first switching trigger is connected to the single output of the second Mutation trigger subsequent discharge,

additional - zero - 1 input: A switching switching trigger is connected to a single output of a second switching trigger of the previous bit, zero inputs of a second switching trigger are connected to zero and a single output of a second discharge, respectively, additional zero inputs of a second switching trigger with an extra zero and

with the single outputs, respectively, of the second and first switching triggers of the previous bit, one of the zero inputs of each of the switching triggers of each of the register bits is connected to the “Left Shift” signal, and one of the additional: zero outputs — the same triggers are connected to bus signal "Shift right.