SU450174A1 - Variable priority device - Google Patents

Description

one

The invention relates to the field of computing, and in particular, to devices that provide variable priority to interrupt signals in electronic computers.

From: Westpo device of variable priority, containing the priority register, one output of which is connected to the decoder, and the input - to the left output of the control unit, the second output of which is connected to the nerve | M input of the counter.

In order to reduce the equipment of the device, it contains a priority interrupt discharge detection unit and a cyclic shift register, with another output of the priority register connected to the second counter input, the third input of which is connected to one output of the interrupt priority detection block, whose inputs are connected to the output , M1 and decoder, counter and cyclic shift register, the input of which is connected to the third output of the control unit, and the input of the control unit is connected to another output of the detection unit, priority og discharge interrupt.

The block diagram of the device shown in the drawing.

The variable priority device contains: priority register 1, decoder 2, block 3 for detecting the priority of the interrupt, counter 4, cyclic shift register 5, control block 6.

The device works as follows. In priority register 1, the code corresponding to the number of the cyclic shift register 5, which is associated with which the interrupt signal should have the highest priority, is programmatically zoomed. The cyclic shift register 5 and counter 4 are set to "O.

When one or several interrupt signals are received, the corresponding bits of the cyclic shift register 5 are set to "1, the execution of the current program is interrupted and the control unit 6 starts to work, as a result of which the contents of the priority register 1 are entered into the counter 4, and the contents of the cyclic shift register 5 begin to shift towards the older bit.

At the same time, after each clock cycle the unit 3 detects the priority interruption bit, the current state of a certain bit of the cyclic register is analyzed

the shift 5 selected by the code in the priority register 1. Under the zero state of the discharge, the counter 4 is added with "I, the first one of the discharge state of the control unit 6 is turned off, and the contents of the counter 4 are used

as a modulated part of the transition address 1 to the corresponding interrupt program.

Let, for example, the width of priority register 1 and counter 4 be three, and the cyclic, shift register 5 be eight. In priority register 1, code 101 is contained. The interrupt signal is fed to the third bit of the cyclic shift register 5.

Code 101 is transmitted to counter 4, and a shift in the contents of cyclic shift register 5 begins simultaneously with counting the number of shifts in counter 4 (summed with code 101). According to the code, in the priority register 1, the EXHIBITION priority is assigned to the fifth bit of the cyclic shift register 5. Since the ANALYSIS of the contents of the cyclic shift register 5 starts with the bit whose index is specified in the priority register 1, then Max 5, 6, 7, O, 1, and 2 were "O, and in bit 3," 1, after six shifts, the unit detects the priority discharge of interrupt 3 and turns off control unit 6. The code in counter 4 is as follows: 101 +. Since the counter of counter 4 is three, the highest bit of the sum is lost, and the contents of counter 4 correspond to the number of the interrupt bit. With this code, the address of the transition to the interrupting program is formed.

Thus, the code in priority register 1 determines the variable priority values of the interrupt signals.

When programmatically changing the contents of priority register 1, the bit number of cyclic shift register 5 is changed, starting from which it will be analyzed by "O and" 1. Discharges that are separated from the analyzed towards the lower bits of the registers are analyzed later and have a gradually decreasing priority.

The total number of positions of the device priority of each interrupting signal corresponds to the size of the cyclic shift register 5.

Subject invention

A variable priority device containing a priority register, one output of which is connected to the decoder, and the input to the first output of the control unit, the second output of which is connected to the first input of the counter, characterized in that, in order to reduce the equipment, it contains of the priority interrupt and cyclic shift register, and another output of the priority register is connected to the second input of the counter, the third input of which is connected to one output of the block for detecting the priority interrupt, inputs Which is connected to the outputs of the decoder, the counter and the cyclic shift register, the input of which is connected to the third output of the control unit, and the input of the control unit is connected to another output of the priority interrupt detection unit.