SU506854A1 - Variable priority device - Google Patents

Description

(54) DEVICE VARIABLE PRIORITY

one

The invention relates to the field of computing and, in particular, to devices that provide variable priority to interrupt signals in electronic computers.

A variable priority device is known comprising a priority register, the code output of which is connected to the counter code input, a control unit whose outputs are connected to the control inputs of the priority register, cyclic shift register and the counter count input.

In order to reduce the equipment of the device, it contains a unit for analyzing the counter zero and an analysis unit for the high-order bit of the cyclic shift register, the inputs of which are connected to the outputs of the counter and the cyclic shift register, respectively, and the outputs with the corresponding inputs of the control unit.

The block diagram of the proposed device shown in the drawing.

The variable priority device includes a priority register 1, a counter 2, a zero analysis block of counter 3, a cyclic shift register 4, an analysis block for, 1 the high bit of the cyclic shift register 5, and a control block 6.

The device works as follows.

In the priority register 1, the code corresponding to the bit number of the cyclic shift register 4 is programmed in software. The interrupt signal has the highest priority at this moment. The cyclic shift register 4 and counter 2 are set to "O.

When one or more interrupt signals are received, the corresponding bits of the cyclic shift register 4 are set to "1, the current program is interrupted, and the control unit 6 starts operating, as a result of which the contents of priority register 1 are entered into the counter 2 with the reverse code. "1, and the contents of the cyclic shift register 4 begin to shift toward the higher bit. Before the shifts, as well as after each shift cycle, the analyzer block analyzes the current state of the counter 2 by zero analysis. In the non-zero state of the counter 2, the content of the counter is added to "1"; in the zero state, the contents of the priority register 1 are transmitted by the direct code counter 2 and the analysis unit begins to operate at the high-order unit of the cyclic shift register 5. When the high-order bit is in zero, the "2" is added to the counter 2, and the next time is executed for one bit of the cyclic shift register 4 in one hundred ronu

the higher bit, then the analysis of the state of the high bit of the shift register 4 LOR / burns, etc. In the single state of the higher bit, the control unit 6 is turned off, and the contents of counter 2 is used as a modifiable part of the jump address to the corresponding , my program.

Let, for example, the width of priority register 1 and counter 2 be four, and the length of cyclic shift register 4 be sixteen. In priority register 1, code 0101 is contained. The interrupt signal is sent to the third bit of cyclic shift register 4.

The contents of the priority register 1 are transferred by a reverse code to counter 2, and one is added to the contents of counter 2. As a result, the counter will be code 1011.

Shifts of the contents of the cyclic register of shift 4 begin simultaneously with the count of the number of shifts in counter 2 (summation with code 1011) and analysis of its contents to zero. After performing five shifts in the counter 2, the “O” most senior priority of the cyclic shift register 4, defined by the code in the priority register 1, will move to the place of the high register register 4, and the unit in the third digit of the cyclic shift register 4 will move to the fourteenth bit. Since code 0101 (5) is in priority register 1, the location of the interrupt signals in order of priority will be the following: "5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 , O, 1, 2, 3, 4.

Code 0101 from priority register 1 is written to counter 2, after which shifts in the contents of cyclic shift register 4 will be continued with a count of the number of shifts (summation with code 0101) and analysis per unit of high-order bit.

If the interrupt signals with the numbers "5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, O, 1, 2 have not been received, then in o-13 bits of the cyclic shift register 4 will be zeros. After performing fourteen shifts, the analysis unit is triggered by a unit of the highest bit of the cyclic shift register 5 and turns off the control unit 6.

The code in counter 2 will be: 0101 + 1110 10011. Since the counter size of 2 is four, the most significant bit of the sum is lost, and the contents of counter 2 correspond to the number of the interrupt bit. This code forms the address of the transition to the interrupting program.

The code in priority register 1 identifies the variable priority values of the interrupt signals.

When programmatically changing the content of 5 register 1, the bit number of the cyclic shift register 4 is changed, the value of which is shifted to the most significant bit of the register, starting from which its analysis will be performed on "O and" 1. Discharges distant from the analyzed in the direction of the lower bits of the register are analyzed later and have a gradually decreasing priority.

The total number of device priority positions and each interrupting signal corresponds to the size of the cyclic shift register 4.

The speed of the known and considered device, i.e. the response time to the interrupt signal, depends both on the bit number of the interrupt signal and on the code in the priority register.

If we take the time of one shift cycle and transfer between registers in 0.2 microseconds, then the response time delay in the known device is from 0.2 to 3.2 microseconds, depending on the code in the priority register 1 and the interrupt number, the device under consideration is, respectively, from 0.4 to 6.4 microseconds. With increasing operating frequency

0 items this time will decrease. For computing systems whose temporal characteristics allow the use of a known device, this difference in response time is not significant.

Claims (1)

Invention Formula A variable priority device containing a priority register, the code output of which is connected to the code input of the counter, the control unit whose outputs are connected with the control inputs of the priority register, the cyclic shift register and the counter count input, characterized in that, in order to reduce the equipment, it contains a counter zero analysis unit and per unit of higher order cyclic shift register, the inputs of which are connected to the outputs of the counter and cyclic shift register, respectively, and the outputs with the corresponding inputs of the control unit.