SU1608651A1 - Device for computing sine function - Google Patents

Abstract

The invention relates to computing and can be used in specialized computers. The aim of the invention is to increase speed by directly checking the convergence of the iterative process. The device contains the first switch 1, the second switch 2, the first register 3, the second register 4, the first register-shifter 5, the second register-shifter 6, the third register-shifter 7, the first adder 8, the second adder 9, the first block 10.1 of the reference memory function values, the second block 10.2 of the memory of the function reference values, block 11 of the inversion of bits, the first element AND 12, the second element AND 13, the element OR 14, the element NOT 15, the element OR-NOT 16, the input 17 the lower bits of the argument, clock input 18, start input 19, input of the 20 most significant bits of the argument, exit 21 of the signs when finished and calculations, the output 22 of the cosine, sine output 23. 1 il.

Description

The invention relates to computing and can be used in specialized computers.

The aim of the invention is to increase speed by directly checking the convergence of the iterative process.

The drawing shows the functional diagram of the device.

The device contains the first 1, second 2 switches, the first 3 and second 4 registers, the first 5, the second 6 and the third 7 shift registers, the first 8 and second 9 adders, the first 10.1 and the second 10.2 memory blocks of the function reference values, the inversion unit 11 bits, the first 12 and second 13 elements And the element OR. 14, element NOT 15 element OR-NOT 16, input 17 lower-order arrays, clock input 18,, start 19, start, 20 high-order bits of the argument, output 2J of the sign of the end of calculations, output 22 kosi; and exit .23 sine.

The device operates as follows

in a way.

The device processes (p-I) -digth binary numbers presented in fixed-point format.

The device is based on the following algorithm for computing x functions. cosCf and y sitiq. The value of the positive argument Cp, defined by the binary code hell, a, ..., a „.,

where ar is the discharge of the whole part; a, a, a n - the fractional part of the argument, is represented as

Wed 4-, , .., a + 00, ..,

 P,

t

cj.-n where q & n / 2, q e l, 2, ...,.

The value of Cf is used to determine the fundamental p-bit approximations of the calculated functions x cosCp ,, y sinU. Subsequent calculations are performed using iterative

(ABOUT

(2) O) (A)

, Obtained as a result of the (n-q) -th iteration of the value of x „. y ,,., in

five

g

0

45

50

55

are the desired values of the functions X COSCP and for sinCP with absolute

I - o-

error not exceeding 2.

In the initial state, all bits of the code at the output of the third shift register 7 have a zero value, as a result of which the sign of the end of calculations at the output of the OR-NOT 16 element, which is simultaneously the first output 21 of the device, is equal to one. A single value goes to the control inputs of the first 5 and second 2 switches, ensuring that the information coming to the outputs of the switches passes. their second informational inputs.

At the clock input device 18 continuously receive clock pulses (TI). At the inputs 17 and 20 devices receive lower q. senior Q, argument bits respectively, Po. the value of the code Cf, from blocks 10.1 and 10.2 of the memory of the reference values of the functions, the values x and y are read. The value x goes to the second mapping input of the first switch 1 and then from the output of the first switch 1 to the information input of the first register 3, as well as shifting q bits to the right to the information input of the second register shifting 6. The value y goes to the second information input the second switch 2 and then from the output of the second switch 2 to the information input of the second register 4, as well as shifting by q bits to the right to the input of the second block of the inversion of bits and then to the information input of the first register shift 5.

To perform calculations synchronously with one of the TIs, a Start signal is sent to the input 19 of the device, which passes to the synchronization inputs of the first 5, second 6 and third 7 shift registers, recording the values Cp, -y and X 2, respectively, -, the Start-up signal passes through the element OR 14, having entered, in registers 3 and 4, the values of x and y, respectively.

With a zero value of all bits of the Cf25 code entered in the third shift register 7, the value of the sign of the end of the calculations remains equal to one, the calculations are not performed and the values of, and y are used as the results of the operation.

5160865

Yri single value at least one digit q value recogn / l

leg

at the output of the element OR-NOT 16 becomes la (equal to zero, providing the information passed from the first information: x inputs of the first 1 and the second 2

who utatopopov,

The inverted value of the sign of the orb of the computation at the second input nepi woo. the element AND 12 becomes equal to one, ensuring the passage of the TI from the input 18 of the device to the transceiver of the first element AND 12.

When the Kth iteration is executed, V V X

f-UK-I UK-1C-1

penetrate the inputs of the first and second components of the first adder 8 and the pulse and second components of the second adder 9, respectively. On you ho / ah the first 8 and second 9 summatoni

PO1

-one

2 and V v + x

 and Y, -u.4 X; (., Z,

which come to the first informational inputs of the first 1 and second 2 co mutators.

Another TI coming to the entrance

X

values are formed.,, - (V “H

18

the device, from the code of the first element and the 12, enters the shift inputs of the retransmitters 5-7, providing on the falling edge of the TI a shift by one bit of information stored in the shift registers 5 and 6, and shifting to the left by one bit of information of the AI, stored in the shift register - TBjе 7, with zeros in the empty bits. With a single

sign

the value of 1I from the output of the nej element i 12 passes to the output of the second element i 13 and further, providing along the leading edge. tee bend into registers, respectively, the values 4eh x and y | according to expressions (1) and (2). With a zero value of the VALUE ASU. The contents of the first 3 and second 4 registers do not change.

The calculation process continues.

before

moment when as a result of vyp.olF about

pm lla

the invention

No next iteration, all bits of the third shift register will have a zero value. At the same time, at the output of the OR-NOT 16 element, a single value is generated, which prevents the TI from passing to the output of the first element And 12, and the device will stop working.

A device for computing the functions ufti sincj and cosLf, containing two

/ l

ten

burn

- 15

- 20

25

-

thirty

, but-

35

40

45

50

55

sixteen

adder, two memory blocks of the function reference values, three shift registers and two registers, the inputs of the higher bits of the device argument are connected to the address inputs of the first and second memory blocks of the function reference values, the outputs of the first and second registers are connected to the inputs of the first and second registers. the terms of the first and second adders respectively, the outputs of the first and second shift registers are connected to the inputs of the second terms of the first and second adders, respectively, differing from the fact that due to direct verification of the convergence of the iterative process, two switches are additionally introduced, a bit inversion unit, two AND elements, an OR-NOT element, an OR element and an NOT element, and the device start input is connected to the register synchronization input The first to third pitch-shifters and the first input of the OR element, the clock input of the device is connected to the first input of the first element AND, the output of which is connected to the shift inputs of the register-shifters from first to third and the first input of the second element I, I The lower bits of the device argument are connected to the information input of the third register-shifter, the outputs of which bits are connected to the corresponding inputs of the OR-NOT element, the output of which is connected to the input of the HE element, the output of which is connected to the second input of the first element AND, the output of the senior the bit of the third shift register is connected to the second input of the second element AND, the output of which is connected to. the second input of the OR element, the output of which is connected to the synchronization inputs of the first and second registers, the information inputs of which are connected to the outputs of the first and second switches, respectively, the first information inputs of which are connected to the outputs of the first and second adders, respectively, of the control inputs of the first and second switches the outputs of the OR-NOT element, the output of the first memory block of the reference values of the function is connected to the information input of the second shift register and the second information the input of the first switch, vi: one second 716086518

the first memory block, the reference value, the output of the OR-NOT element is connected to the function, connected to the second information output of the termination feature of the second switch, calculated in the second switch, the second device, the outputs of the first and second outputs of the bit inverter, of the registers connected to the outputs of the course of which is connected to the information of the cosine and sine, respectively, by the oral input of the first register-shift device.

Claims (1)

The invention relates to computer technology and can be used in specialized computers. The aim of the invention is pov-4 ide, 1985, p.137. fig. 3.10. a <e about 21 SU „„ 1608651 d The invention relates to computer technology and can be used in specialized calculators. 5 The aim of the invention is to improve performance by directly checking the convergence of the iterative process.