SU1444758A1 - Digital function converter - Google Patents

Abstract

The invention relates to the field of computer technology and can be used to calculate the complexity of mathematical functions in high-speed specialized processors in many fields of the national economy. The aim of the invention is to expand the scope due to the additional possibility of reproducing monotonically increasing even and odd functions. The digital functional converter consists of the registers of the low and high bits of the argument, the trigger of the sign bit of the argument, the coefficient memory, the memory of the reference function values, five switches, the multiplier, two adders, two elements EXCLUSIVE OR, and two elements I. 1 silt 1 tab. o (l

Description

Oiiik 4 U SP 00

The invention relates to computing and can be used to calculate complex mathematical functions in high-speed specialized processors.

The purpose of the invention is to expand the field of application of the digital functional converter due to the additional reproduction of monotonously increasing even and odd functions.

The drawing shows a block diagram of a digital functional Converter.

The digital function converter contains the register of 1 lower order bits of the argument, the register of 2 most significant bits of the argument, trigger of 3 digits. block 4 of coefficient memory and block 5 of memory of reference values of function, switches 6-10, multiplier 11, two adders 12 and 13, input 14 sets a killer-increasing function, input 15 sets an even-odd function two elements EXCEPTOR OR 16 and 17 and two elements and 18 and 19.

The algorithm of the digital functional converter is as follows:

Yj-i (X) y, ®Yj (x;, j) ®y @ 4Yj; (X;, j.) + -I-W © (q LC) + Ur lh + Il hy;

35

40

45

de X cTj Ho .® Xcg. ;

XMAJJ P ®

{i (X | i, A ..; K) XMK .. C / C | b ,; Ho is the sign of the argument; hj - unit weight

operand; TO; -.Tilt coefficient; j and i are the indices, respectively, of the number of the reference value and the point between the reference values;

Ur is the sign of the function, W is the conjunction of the values, the signals at input 14, input 15 and Q is the sum modulo two signals

on. entrance i 14 and ho; P - the sum modulo two signals at the input 14 and X ,,. Digital functionality of the Converter works as follows.

With the help of external signals indicating the type of reproducible function, as well as the value of the sign bit

55

0 5

°

five

0

five

five

argument in logic gates And 19 and 18 and two logic gates EXCLUSIVE OR 16 and 17 generate control signals that are fed to the control inputs of switches 6, 8, 9 and 10 and provide the calculated functions according to a given algorithm.

The algorithm of the digital functional converter is shown in the table.

Claims (1)

Invention Formula Digital function converter containing the register of the younger ones. argument bits, the register of the leading bits of the argument, the character trigger, five switches, the coefficient memory block, the function reference memory block, the multiplier and the first adder, the device argument input connected to the information inputs of the lower and higher bits, the input of the symbol argument of the device is connected to the installation input of the sign trigger, the direct output of which is connected to the control input of the first switch, the first and second information inputs of which are connected respectively to the direct and inverse The outputs of the register of the higher bits of the argument, the direct and inverse outputs of the register of the lower bits of the argument are connected respectively to the first and second information inputs of the second switch, the output of which is connected to the input of the first multiplier of the multiplier, the second input of which is connected to the direct output of the coefficient memory block and the first information input of the third switch, the second information input of which is connected to the inverse output of the coefficient memory, the address input of which is connected to the code of the first the switch and the address input of the memory of the reference function values, the direct and inverse codes of which are connected respectively to the first and second information inputs of the fourth switch, the outputs of the third and fourth switches are connected to the inputs of the first and second components of the first adder, the direct and inverse outputs of the multiplier connected to the first and second inputs of the fifth switch, respectively, in order to expand the field of application through additional reproduction monotonously augmenting even and odd functions, two EXCLUSIVE OR elements are entered into it, two AND elements and a second adder, the input setting the even-odd function of the device connected to the first inputs of the first and second elements AND, the second inputs of which are connected to the direct output of the sign trigger , the inverse output of which is connected to the first input of the first element EXCLUSIVE OR, the second input of which is connected to the input of the assignment of the decreasing-increasing function of the device, the third input of the first element AND and the first input of the second the first element, the second input of which is connected to the direct input of the sign trigger, the output of the first element EXCLUSIVE OR is connected to the control input of the second switch; and fifth switches, the outputs of the first and second elements And are connected to the input of the third term of the first adder, the output of which is connected to the input of the first term of the second adder, the input of the second term of which connects The output of the second adder is connected to the output of the value of the function of the device, the output of the sign of the function of which is connected to the output of the second element I.