SU547767A2 - Variable priority device - Google Patents

Description

(54) DEVICE VARIABLE PRIORITY

one

The invention relates to computing, in particular, to devices that provide a variable priority of interrupt signals in electronic computing machines.

A variable priority device is known that contains a priority register, one output of which is connected to the decoder, and the input to the first output of the control unit, the second output of which is connected to the first input of the counter. The output of the priority register is connected to the second input of the counter, the third input of which is connected to one output of the preemptive bit detection unit. The inputs of the latter are connected to the output of the decoder, the counter and the nickel shift register, the input of which is connected to the third output of the control unit, and the output of the control unit is connected to another output of the preemptive bit detection unit.

This device allows using a single priority register, in which a code is entered corresponding to the bit number of the cyclic shift register associated with

which the interrupt signal should have at the moment the highest priority, the decoder and the priority interrupt detection unit of the interrupt, serving for sequential polling and detecting the priority interrupt discharge, and the counter for the automatic form: checking the transition address to the interrupting program, implementing the program changing the priority of interrupt signals.

The number of possible device priority positions and each interrupt signal does not exceed the size of the cyclic shift register; this limits the control flexibility and control capabilities of control systems using even this invention.

The purpose of the invention is to expand the functional possibilities by increasing the number of priority positions and interrupt signals.

This is achieved by introducing a shift direction trigger, the output of which is connected to the input of the control unit, and a block for inverting the contents of the counter, connected by two-way form communications, to the control input, to the output of the control unit. The drawing shows the block diagram of the device. The variable priority device contains priority register 1, decoder 2, block 3, detection of priority preemptive bits, counter 4, cyclic shift register 5, control unit 6, shift direction trigger 7, block 8 invert the contents of the counter. The device operates as follows. Priority register 1 programmatically enters the code corresponding to the bit number of cyclic shift register 5, the interrupt signal associated with which should have the highest priority at the moment. At the same time, the shift direction trigger 7 is entered into a code corresponding to the shift direction of the cyclic shift register to the left or right when searching for the priority interrupt level, i.e., the code defining the interrogation sequence of the interruption intervals, starting from the fixed code in the priority register 1 most significant bit left or right. Simultaneously with entering the code into priority register 1 and trigger 7, cyclic shift register 5 and counter 4 are set to O. When one or more interrupt signals are received, the corresponding bits of cyclic shift register 5 are set to 1, the execution of the current program is interrupted and the control unit 6 starts up as a result, the holding of priority register 1 is entered into counter 4 with a forward or reverse code depending on the state of trigger 7, and the contents of cyclic shift register 5 begins to shift to the left in or right. At the same time, after each clock cycle, the interrupt priority detection unit 3 detects the current clock T05 of a certain bit of the cyclic shift register 5 selected by the code in the priority register 1. With the discharge state on the counter 4, 1 is added, with a single discharge state yes - the control unit 6 is turned off, and the contents of counter 4 in the forward or reverse code, depending on the state of trigger 7, are used as the modulated part of the transition address to the corresponding interrupting program. For example, the priority register 1 and counter 4 are three, and the cyclic shift register is 5 eight; About the state of the trigger 7 you call the transfer from the priority register 1 to the counter 4 with a direct code, shifts the contents of the cyclic shift register 5 to the left and using the result obtained in the counter 4 in the direct code i the status of the trigger 7 causes the transfer from the register 1 to the counter 4 to reverse By code shifting cyclic shift register 5 to the right and 1 inverting the result obtained in counter 4, priority register 1 contains code 101, trigger 7 is in state A. The interrupt signal is received in the third position of cyclic shift register 5. 101 is transmitted to the counter 4 straight code and starts a cyclic shift 5 register contents left simultaneously with the account number of shifts in the counter 4 (summing with the code 101). According to the code in the priority register 1, the highest priority is assigned to the fifth bit of the cyclic shift register 5. Since the analysis of the contents of the cyclic shift register 5 begins with a bit, the number of which is specified in the priority register 1, then in bits 5, 6, 7, O, 1 and 2 were O, and in the third bit - 1, after six shifts, block 3 detects the priority of the interrupt and triggers a signal to the control unit 6 to stop the register shifts 5 and end the count by counter 4. Code in the counter 4 will be 101 + 110 1011. Since the discharge is low The counter is equal to three, the most significant bit of the sum is lost, and the contents of the counter correspond to the number of the interrupt bit. This code forms the address of the transition to the interrupting program. Thus, with code 101 in priority register 1 and O, state of trigger 7, the sequence of priority polling of cyclic shift register bits 5 (i.e. the priority position) is 5, 6, 7, O, 1, 2, 3, 4 For example, trigger 7 is in state 1, in priority register 1 — code 101, the interrupt signal is received in the third bit of cyclic shift register 5. Code 101 is transmitted to counter 4 by a reverse code and the shift of cyclic shift register 5 to the right begins simultaneously with the count the number of shifts in the counter (summation with code 0 ten). The priority analysis of the interrupt bits is performed in the sequence 5, 4, 3. If in bits 5 and 4 were O, and in bit 3 - I, then after two shifts, the block 3 for detecting the priority interrupt bit will work and give a signal to the block control 6 to stop shifting the cyclic shift register 5 and ending the counting by the counter 4. The counter code will be 010 + 010 100. Since the trigger 7 is in the IL state, the signal from the control unit 6 will trigger the inverter counter 8 and change the code to counter on the back, i.e. 011. The contents of the counter 4 with sponds discharge interrupt number. This code forms the address of the transition to the interrupting program.

Thus, with code 10-1 in the priority register 1 and 1 of the trigger state 7, the sequence of priority polling of the cyclic shift register 5 is 5, 4, 3, 2, 1, O, 7. 6.

When the program changes the contents of the priority register 1 and trigger 7, the bit number of the cyclic shift register 5 changes, starting with which it will be analyzed for Q and 1, as well as the sequence of priority polling of bits. Discharges that are separated from the analyzed towards the younger ones at O of the trigger 7, or those located to the side of the older ones at 1 trigger 7, are analyzed later and have a gradually decreasing priority.

The total number of device priority positions corresponds to twice the width of the cyclic shift register 5.

Increasing the number of positive sig-

Interrupt routing allows you to extend the number of states in control systems that differ in response to interrupt signals, which expands control functions and increases control flexibility.

The implementation of the automatic generation of the exit address of the interrupting program simultaneously with the interrogation of interrupt signals makes it possible to provide one of the main requirements for modern computer control devices, without significant hardware costs, to increase the automation of interrupt processing.

Claims (1)

Formula of the invention, and The device is a variable priority auth. swith No. 450174, characterized in that, in order to expand the functionality of the device by increasing the number of priority positions and interrupt signals, a shift direction trigger has been introduced, the output of which is connected to the input of the control unit, and a counter content inverting unit connected by two-way information links with the counter, and the controller - with the output of the control unit.